SN74ALS994NT


     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 • • • • DW OR NT PACKAGE (TOP VIEW) 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs OERB 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND description This 10-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The ten latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches passes back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs. OERB does not affect the internal operation of the latches; however, precautions should be taken to avoid a bus conflict. The SN74ALS994 is characterized for operation from 0°C to 70°C. logic symbol† 1 OERB LE 1D 13 2 EN2 C1 1D 23 2 2D 3D 4D 5D 6D 7D 8D 9D 10D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright  1995, Texas Instruments Incorporated     !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2−1 

     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 logic diagram (positive logic) OERB LE 1D 1 13 2 23 1D 1Q C1 To Nine Other Channels timing diagram Data Bus Input Data tsu Read Back Input Data th LE tsu† tdis OERB tpd tpd Q † This setup time ensures that the read-back circuit will not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (OERB and LE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 

     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current tw Pulse duration, LE high tsu Setup time High-level input voltage MIN NOM MAX 4.5 5 5.5 2 Q −2.6 D −0.4 Q 24 D 8 10 th Hold time, data after LE↓ TA Operating free-air temperature † This setup time ensures that the read-back circuit will not create a conflict on the input data bus. V V 0.8 Data before LE↓ Data before OERB↓† UNIT V mA mA ns 10 ns 10 5 ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS MIN TYP‡ MAX UNIT −1.2 V All outputs VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = − 18 mA IOH = − 0.4 mA VCC − 2 Q VCC = 4.5 V, IOH = − 2.6 mA 2.4 0.4 VCC = 4.5 V IOL = 4 mA IOL = 8 mA 0.25 D 0.35 0.5 0.25 0.4 VCC = 4.5 V IOL = 12 mA IOL = 24 mA 0.35 0.5 D inputs VCC = 5.5 V VI = 7 V VI = 5.5 V IIH OERB, LE D inputs§ VCC = 5.5 V, VI = 2.7 V IIL OERB, LE D inputs§ VCC = 5.5 V, VI = 0.4 V IO¶ VCC = 5.5 V, VO = 2.25 V ICC VCC = 5.5 V, OERB high Q outputs high 30 50 Q outputs low 52 82 VOH VOL Q OERB, LE II V 3.2 V 0.1 0.1 20 20 mA µA A −0.1 −0.1 −30 −112 mA mA mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−3 

     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q ten‡ tdis§ OERB D VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX† MIN MAX 3 14 4 18 6 21 8 27 4 21 2 16 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ ten = tPZH or tPZL § tdis = tPHZ or tPLZ 2−4 UNIT 

     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V S1 1 kΩ Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 Ω LOAD CIRCUIT FOR Q OUTPUTS 1 kΩ LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 3.5 V High-Level Pulse 1.3 V 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.3 V 1.3 V 0.3 V 3.5 V Output Control (low-level enabling) 1.3 V tPHL tPLH 1.3 V VOL tPLH tPHL Out-of-Phase Output (see Note B) Waveform 1 S1 Closed (see Note C) VOH 1.3 V tPLZ 1.3 V tPZH Waveform 2 S1 Open (see Note C) 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES [3.5 V 1.3 V tPHZ VOH 1.3 V 0.3 V tPZL 1.3 V 0.3 V In-Phase Output 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Input 3.5 V Low-Level Pulse 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. When measuring propagation delay times of 3-state outputs, switch S1 is open. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. Figure 1. Load Circuits and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−5 

     
     SDAS237A − OCTOBER 1984 − REVISED JANUARY 1995 2−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 29-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74ALS994DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS994 SN74ALS994NT LIFEBUY PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS994NT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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