SN74AS805BDWRE4








    
 SDAS023C − DECEMBER 1982 − REVISED JANUARY 1995 SN54ALS805A, SN54AS805B . . . J PACKAGE SN74ALS805A, SN74AS805B . . . DW OR N PACKAGE (TOP VIEW) High Capacitive-Drive Capability ′ALS805A Has Typical Delay Time of 4.2 ns (CL = 50 pF) and Typical Power Dissipation of 4.2 mW Per Gate ′AS805B Has Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of 12 mW Per Gate Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs • • 1A 1B 1Y 2A 2B 2Y 3A 3B 3Y GND description These devices contain six independent 2-input NOR drivers. They perform the Boolean functions Y = A + B or Y = A • B in positive logic. OUTPUT Y H X L X H L L L H logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 1 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 6B 6A 6Y 5B 5A 5Y 4B 4A 4Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6A 6Y 5B 5A 5Y 3Y GND 4Y 4A 4B B 2 1Y 1B 1A VCC 2A 2B 2Y 3A 3B FUNCTION TABLE (each driver) INPUTS 20 SN54ALS805A, SN54AS805B . . . FK PACKAGE (TOP VIEW) The SN54ALS805A and SN54AS805B are characterized for operation over the full military temperature range of − 55°C to 125°C. The SN74ALS805A and SN74AS805B are characterized for operation from 0°C to 70°C. A 1 6B • • logic diagram (positive logic) ≥1 3 4 6 5 1A 1Y 1B 2A 2Y 2B 7 9 8 3A 3Y 3B 12 11 13 4A 4Y 4B 15 14 16 5A 5Y 5B 18 17 19 6Y 6A 6B 1 2 3 1Y 4 5 6 2Y 7 8 9 3Y 12 13 11 4Y 15 16 14 5Y 18 19 17 6Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright  1995, Texas Instruments Incorporated   !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 







    
 SDAS023C − DECEMBER 1982 − REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS805A . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74ALS805A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS805A SN74ALS805A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current −12 −15 mA IOL TA Low-level output current 24 mA 70 °C High-level input voltage 2 2 V 12 Operating free-air temperature −55 125 V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54ALS805A TYP‡ MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = −18 mA IOH = − 0.4 mA VCC = 4.5 V IOH = − 3 mA IOH = − 12 mA VOL VCC = 4.5 V II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO§ VCC = 5.5 V, VCC = 5.5 V, ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, SN74ALS805A TYP‡ MAX MIN −1.2 VCC − 2 2.4 −1.2 VCC − 2 2.4 3.2 V 3.2 V 2 IOH = − 15 mA IOL = 12 mA UNIT 2 0.25 IOL = 24 mA VI = 7 V 0.4 0.25 0.4 0.35 0.5 0.1 VI = 2.7 V VI = 0.4 V VO = 2.25 V VI = 0 −20 mA 20 20 µA −0.1 −0.1 mA −112 mA mA −112 −30 2 4 2 4 8 14 8 14 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 2 VI = 4.5 V 0.1 V • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 







    
 SDAS023C − DECEMBER 1982 − REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† TO (OUTPUT) SN54ALS805A tPLH tPHL A or B UNIT SN74ALS805A MIN MAX MIN MAX 1 12 2 7 1 9 2 8 Y ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS805B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74AS805B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions§ SN54AS805B SN74AS805B MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current −40 −48 mA 40 48 mA 70 °C High-level input voltage 2 IOL Low-level output current TA Operating free-air temperature −55 § These high sink- or source-current devices are not recommended for use above 40 MHz. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2 125 0 V V 3 







    
 SDAS023C − DECEMBER 1982 − REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54AS805B TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = −18 mA IOH = − 2 mA VCC = 4.5 V IOH = − 3 mA IOH = − 40 mA VOL VCC = 4.5 V II IIH VCC = 5.5 V, VCC = 5.5 V, IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, SN74AS805B TYP† MAX MIN −1.2 VCC − 2 2.4 −1.2 VCC − 2 2.4 3.2 V 3.2 V 2 IOH = − 48 mA IOL = 40 mA UNIT 2 0.25 IOL = 48 mA VI = 7 V 0.5 0.35 0.5 0.1 VI = 2.7 V VI = 0.4 V VO = 2.25 V VI = 0 −50 0.1 mA 20 20 µA −0.5 −0.5 mA −200 mA mA −200 −50 6.5 10 6.5 10 20 32 20 32 VI = 4.5 V V mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX§ SN54AS805B tPLH tPHL A or B Y SN74AS805B MIN MAX MIN MAX 1 4.8 1 4.3 1 4.8 1 4.3 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT ns 







    
 SDAS023C − DECEMBER 1982 − REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point From Output Under Test LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 3.5 V Input tPZH 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output VOL 0.3 V 1.3 V 1.3 V VOL tPLH tPHL VOH 1.3 V 1.3 V [3.5 V 1.3 V tPHZ Waveform 2 S1 Open (see Note B) 1.3 V VOH Out-of-Phase Output (see Note C) 0.3 V [0 V 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) 5962-87794012A ACTIVE 5962-8869401SA SN54ALS805AJ Package Type Package Pins Package Drawing Qty 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) TBD POST-PLATE N / A for Pkg Type -55 to 125 Device Marking (4/5) LCCC FK 20 OBSOLETE CFP W 20 TBD Call TI Call TI -55 to 125 OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 596287794012A SNJ54AS 805BFK SN74ALS805ADWR OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74ALS805ADWRE4 OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74ALS805ADWRG4 OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 SN74ALS805AN3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SN74AS805BDW OBSOLETE SOIC DW 20 TBD Call TI Call TI 0 to 70 AS805B SN74AS805BN SN74AS805BN OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70 SNJ54ALS805AFK OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 SNJ54ALS805AJ OBSOLETE CDIP J 20 TBD Call TI Call TI -55 to 125 SNJ54AS805BFK ACTIVE LCCC FK 20 TBD POST-PLATE N / A for Pkg Type -55 to 125 1 596287794012A SNJ54AS 805BFK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN54ALS805A, SN54AS805B, SN74ALS805A, SN74AS805B : • Catalog: SN74ALS805A, SN74AS805B • Military: SN54ALS805A, SN54AS805B NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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