SN74AS825ADW

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 • • • • Functionally Equivalent to AMD’s AM29825 Improved IOH Specifications Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs SN54AS825A . . . JT PACKAGE SN74AS825A . . . DW OR NT PACKAGE (TOP VIEW) OE1 OE2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND description These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers. Multiuser buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without interface or pullup components. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLKEN CLK 1D OE2 OE1 NC VCC SN54AS825A . . . FK PACKAGE (TOP VIEW) 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 4 2D 3D 4D NC 5D 6D 7D 19 11 12 13 14 15 16 17 18 2Q 3Q 4Q NC 5Q 6Q 7Q 8D CLR GND NC CLK CLKEN 8Q With the clock-enable (CLKEN) input low, the eight D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. These devices have noninverting data (D) inputs. Taking the clear (CLR) input low causes the eight Q outputs to go low independently of the clock. 1 OE3 1Q • • • NC – No internal connection The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS825A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AS825A is characterized for operation from 0°C to 70°C. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 FUNCTION TABLE (each flip-flop) INPUTS OE† D OUTPUT Q CLR CLKEN CLK L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q0 H X X X X † OE = H if any of OE1, OE2, or OE3 are high. OE = L if all of OE1, OE2, or OE3 are low. Z logic symbol‡ OE1 OE2 OE3 CLR CLKEN CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 & 2 EN 23 11 14 13 3 R G1 1C2 22 2D 4 21 5 20 6 19 7 18 8 17 9 16 10 15 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 logic diagram (positive logic) OE1 OE2 OE3 CLR CLKEN CLK 1 2 23 11 14 R 13 C1 1D 3 22 1Q 1D To Seven Other Channels Pin numbers shown are for the DW, JT, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 recommended operating conditions SN54AS825A SN74AS825A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current – 24 – 24 mA IOL Low-level output current 32 48 mA tw* Pulse duration High-level input voltage 2 CLR low CLK high or low CLR inactive tsu* Data Setup time before CLK↑ CLKEN high or low th* TA Hold time after CLK↑ CLKEN low or data Operating free-air temperature 2 7 4 9.5 8 8 8 7 6 10 6 0 V ns ns 0 – 55 125 V ns 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4 4.5 5V IOH = – 15 mA IOH = – 24 mA VOL 5V VCC = 4 4.5 IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VI = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V ICC VCC = 5.5 V VOH SN54AS825A MIN TYP† MAX TEST CONDITIONS SN74AS825A MIN TYP† MAX – 1.2 VCC – 2 2.4 – 1.2 VCC – 2 2.4 3.2 2 UNIT V V 3.2 2 0.3 0.5 0.35 V µA 50 50 – 50 – 50 µA 0.1 0.1 mA 20 20 µA – 0.5 mA – 112 mA – 0.5 – 30 0.5 – 112 – 30 Outputs high 45 73 45 73 Outputs low 56 90 56 90 Outputs disabled 59 95 59 95 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† SN54AS825A UNIT SN74AS825A MIN MAX MIN MAX 3.5 9 3.5 7.5 3.5 13.5 3.5 13 3.5 16.5 3.5 15.5 4 12 4 11 4 13 4 12 1 10 1.5 8 tPLZ 1 10 1.5 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 8 tPLH tPHL tPHL tPZH tPZL tPHZ CLK An Q Any CLR Any Q OE An Q Any OE Any Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns 5 SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B – JUNE 1984 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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