SN74AUC1G79YZPR

Product Folder Order Now Support & Community Tools & Software Technical Documents SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 SN74AUC1G79 Single Positive-Edge-Triggered D-type Flip-Flop 1 Features 3 Description • This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. 1 • • • • • • • • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V Low Power Consumption, 10-µA Maximum ICC ±8-mA Output Drive at 1.8 V When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Device Information(1) 2 Applications • • • • • • • • • • • • PART NUMBER AV Receiver Audio Dock: Portable Blu-Ray Player and Home Theater Embedded PC MP3 Player/Recorder (Portable Audio) Personal Digital Assistant (PDA) Power: Telecom/Server AC/DC Supply: Single Controller: Analog and Digital Solid State Drive (SSD): Client and Enterprise TV: LCD/Digital and High-Definition (HDTV) Tablet: Enterprise Video Analytics: Server Wireless Headset, Keyboard, and Mouse PACKAGE BODY SIZE (NOM) SN74AUC1G79DBV SOT-23 (5) 2.90 mm × 1.60 mm SN74AUC1G79DCK SC70 (5) 2.00 mm × 1.25 mm SN74AUC1G79YZP 1.75 mm × 1.25 mm DSBGA (5) (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) CLK CLK Q D Q D 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 5 6 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics: CL = 15 pF ...................... Switching Characteristics: CL = 30 pF ...................... 6.9 Operating Characteristics.......................................... 6 7 8 Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Functional Block Diagram ......................................... 8 8.2 Device Functional Modes.......................................... 8 9 Device and Documentation Support.................... 9 9.1 9.2 9.3 9.4 9.5 9.6 Documentation Support ............................................ Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 9 9 9 9 9 9 10 Mechanical, Packaging, and Orderable Information ............................................................. 9 4 Revision History Changes from Revision K (April 2007) to Revision L Page • Deleted DRY package throughout data sheet........................................................................................................................ 1 • Added Applications, Device Information table, Pin Configuration and Functions, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.............................................................................. 1 • Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data sheet ...................................................................................................................................................................................... 1 • Changed pin names in the pinout diagram for the YZP package, from: "A" to:"D," from:"B" to:"CLK," and from:"Y" to: "Q" 3 2 Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 SN74AUC1G79 www.ti.com SCES387L – MARCH 2002 – REVISED JUNE 2017 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View D 1 CLK 2 5 3 GND 4 DCK Package 5-Pin SC70 Top View VCC D 1 CLK 2 GND 3 5 VCC 4 Q Q YZP Package 5-Pin DSBGA Bottom View 1 2 C GND Q B CLK A D VCC Not to scale See mechanical drawings for dimensions. Pin Functions PIN NAME DBV, DCK YZP CLK 2 B1 D 1 GND 3 Q 4 VCC 5 I/O DESCRIPTION I Clock input A1 I Data input C1 — Ground C2 O Latched output A2 — Positive supply Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 3 SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 3.6 V (2) VI Input voltage –0.5 3.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 3.6 V VO Output voltage range (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) Storage temperature –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine Model (A115-A) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage MIN MAX UNIT 0.8 2.7 V VCC VCC = 1.1 V to 1.95 V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 0.8 V VIL Low-level input voltage V 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 V VI Input voltage 0 3.6 V VO Output voltage 0 VCC V IOH IOL (1) 4 High-level output current Low-level output current VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V 9 mA mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004. Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 SN74AUC1G79 www.ti.com SCES387L – MARCH 2002 – REVISED JUNE 2017 Recommended Operating Conditions (continued) See(1) MIN Δt/Δv Input transition rise or fall rate TA Operating free-air temperature MAX UNIT 20 ns/V 85 °C –40 6.4 Thermal Information SN74AUC1G79 THERMAL METRIC (1) RθJA (1) DBV (SOT-23) DCK (SC70) YZP (DSBGA) 5 PINS 5 PINS 5 PINS 206 252 132 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II VCC MIN TYP (1) MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 μA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA ICC VI = VCC or GND, 0.8 V to 2.7 V 10 µA Ci VI = VCC or GND (1) D or CLK input TEST CONDITIONS IO = 0 2.5 V 2.5 µF All typical values are at TA = 25°C. 6.6 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V TYP VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V ± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V MIN MAX MIN MAX MIN MAX MIN MAX 200 225 250 275 UNIT MHz fclock Clock frequency 50 tw Pulse duration, CLK high or low 4.6 1.7 1.7 1.7 1.7 ns tsu Setup time before CLK↑, data high or low 1.5 1.1 0.7 0.7 0.5 ns th Hold time, data after CLK↑ 0 0 0 0.1 ns 0 Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 ns 5 SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 www.ti.com 6.7 Switching Characteristics: CL = 15 pF over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) CLK Q VCC = 0.8 V fmax tpd VCC = 1.2 V ± 0.1 V TYP MIN 50 200 5 1 MAX VCC = 1.5 V ± 0.1 V MIN MAX 225 3.9 VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V TYP MAX 1 1.9 250 0.8 2.5 0.3 MIN UNIT MAX 275 0.3 MHz 1.3 ns 6.8 Switching Characteristics: CL = 30 pF over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER VCC = 1.8 V ± 0.15 V TO (OUTPUT) MIN fmax VCC = 2.5 V ± 0.2 V TYP MAX 250 tpd CLK Q 0.8 275 1.5 2.4 UNIT MIN MAX 0.6 ns 1.8 ns 6.9 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 18 18 18 18.5 20.5 Submit Documentation Feedback UNIT pF Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 SN74AUC1G79 www.ti.com SCES387L – MARCH 2002 – REVISED JUNE 2017 7 Parameter Measurement Information TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tW tsu VCC Input VCC/2 VCC/2 th VCC Data Input VCC/2 VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPLH VOH Output VCC/2 VOL tPHL VCC/2 0V VCC VCC/2 tPZH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VCC/2 tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL tPHL VCC/2 VCC Output Control VOL + VD VOL tPHZ VCC/2 VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, slew rate ³ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 7 SN74AUC1G79 SCES387L – MARCH 2002 – REVISED JUNE 2017 www.ti.com 8 Detailed Description 8.1 Functional Block Diagram CLK CLK Q Q D D Figure 2. Logic Diagram (Positive Logic) 8.2 Device Functional Modes Table 1 lists the functional modes of the SN74AUC1G79. Table 1. Function Table INPUTS 8 CLK D OUTPUT Q ↑ H H ↑ L L L X Q0 Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 SN74AUC1G79 www.ti.com SCES387L – MARCH 2002 – REVISED JUNE 2017 9 Device and Documentation Support 9.1 Documentation Support 9.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs, SCBA004 9.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 9.4 Trademarks NanoFree, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2002–2017, Texas Instruments Incorporated Product Folder Links: SN74AUC1G79 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AUC1G79DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 U79R Samples SN74AUC1G79DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (UR5, URF, URR) Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of