SN74AUC2G53
www.ti.com ................................................................................................................................................ SCES484C – AUGUST 2003 – REVISED JANUARY 2009
SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR
2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER
FEATURES
1
DCT OR DCU PACKAGE
(TOP VIEW)
• Available in the Texas Instruments NanoFree™
Package
• Operates at 0.8 V to 2.7 V
• Sub-1-V Operable
• Low Power Consumption, 10 µA at 2.7 V
• High On-Off Output Voltage Ratio
• High Degree of Linearity
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2
COM
INH
GND
GND
1
8
2
7
3
6
4
5
VCC
Y1
Y2
A
YZP PACKAGE
D
D
C
C
B
B
A
A
2 1
Laser Marking View
1 2
Bump View
YZP TERMINAL ASSIGNMENTS
D
GND
A
C
GND
Y2
B
INH
Y1
A
COM
VCC
1
2
DESCRIPTION/ORDERING INFORMATION
This analog switch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.1-V to 2.7-V VCC
operation.
The SN74AUC2G53 can handle both analog and digital signals. The device permits signals with amplitudes of up
to VCC (peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2009, Texas Instruments Incorporated
SN74AUC2G53
SCES484C – AUGUST 2003 – REVISED JANUARY 2009 ................................................................................................................................................ www.ti.com
ORDERING INFORMATION
TA
PACKAGE
–40C to 85C
(1)
(2)
(3)
(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUC2G53YZPR
_ _ _U4_
SSOP – DCT
Reel of 3000
SN74AUC2G53DCTR
U53_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC2G53DCUR
U53_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
CONTROL
INPUTS
ON
CHANNEL
INH
A
L
L
L
H
Y2
H
X
None
Y1
LOGIC DIAGRAM (POSITIVE LOGIC)
A
5
SW
SW
INH
7
6
1
2
Y1
Y2
COM
NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals may
be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.
SIMPLIFIED SCHEMATIC, EACH SWITCH (SW)
COM
2
Y
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range (2)
–0.5
3.6
V
VI
Input voltage range (2) (3)
–0.5
3.6
V
–0.5
VCC + 0.5
(2) (3)
VI/O
Switch I/O voltage range
IIK
Control input clamp current
VI < 0
II/OK
I/O port diode current
VI/O < 0 or VI/O > VCC
IT
On-state switch current current
VI/O = 0 to VCC
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
(1)
(2)
(3)
(4)
mA
50
mA
50
mA
100
mA
220
DCU package
227
YZP package
102
–65
V
–50
DCT package
Storage temperature range
UNIT
C/W
150
C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V
MIN
MAX
0.8
2.7
V
1.7
VCC = 0.8 V
Low-level input voltage
V
VCC
0.65 נVCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VIL
UNIT
0
0.35 נVCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
V
0.7
VI/O
I/O port voltage
0
VCC
V
VI
Control input voltage
0
3.6
V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 0.8 V to 1.6 V
20
VCC = 1.65 V to 1.95 V
10
VCC = 2.3 V to 2.7 V
(1)
ns/V
3.5
–40
85
C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
On-state switch resistance
ron(p)
(1)
Peak on resistance
TEST CONDITIONS
VI = VCC or GND,
VINH = VIL
(see Figure 1 and
Figure 2)
VI = VCC to GND,
VINH = VIL
(see Figure 1 and
Figure 2)
IS = 4 mA
IS = 8 mA
IS = 4 mA
IS = 8 mA
VCC
MIN TYP (1)
1.1 V
MAX
UNIT
40
1.65 V
12.5
20
2.3 V
6
15
1.1 V
131
180
1.65 V
32
80
2.3 V
15
20
Ω
Ω
TA = 25C
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
VCC
MAX
Difference of on-state resistance
between switches
2.3 V
1
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND, or
VI = GND and VO = VCC,
VINH = VIH (see Figure 3)
2.7 V
(1)
IS(on)
On-state switch leakage current
VI = VCC or GND, VINH = VIL,
VO = Open (see Figure 4)
2.7 V
II
Control input current
VC = VCC or GND
2.7 V
5
µA
ICC
Supply current
VC = VCC or GND
2.7 V
10
µA
Cic
Control input capacitance
Δron
IS = 4 mA
IS = 8 mA
1.1 V
4
1.65 V
1
UNIT
VI = VCC to GND,
VC = VIH
(see Figure 1 and
Figure 2)
1
0.1
1
0.1 (1)
2.5 V
Cio(off)
Switch input/output capacitance
Cio(on)
Switch input/output capacitance
Y
2
µA
pF
4.5
2.5 V
µA
pF
3
2.5 V
COM
Ω
9
pF
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 5)
PARAMETER
tpd (1)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
COM or Y
Y or COM
0.3
ten
tdis
ten
tdis
(1)
INH
COM or Y
A
COM or Y
TYP
VCC = 1.2 V
0.1 V
MIN
MAX
VCC = 1.5 V
0.1 V
MIN
VCC = 1.8 V
0.15 V
MAX
0.3
MIN
TYP
0.3
VCC = 2.5 V
0.2 V
MAX
MIN
0.2
UNIT
MAX
0.1
9.2
0.5
3.5
0.5
2.2
0.5
1
1.9
0.5
1.8
8.1
0.5
4.2
0.5
3.2
0.5
1.9
3.4
0.5
2.6
9.2
0.5
3.6
0.5
2.3
0.5
1.1
1.9
0.5
1.6
10
0.5
3.6
0.5
2.3
0.5
1.1
2
0.5
1.6
ns
ns
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 5)
PARAMETER
tpd (1)
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
COM or Y
Y or COM
INH
COM or Y
A
COM or Y
ten
tdis
(1)
4
VCC = 1.8 V
0.15 V
VCC = 2.5 V
0.2 V
MIN
TYP
MAX
MIN
0.5
1.6
3.1
0.5
2.2
0.5
2.2
3.4
0.5
2.2
0.5
1.6
3
0.5
2.2
0.5
1.6
3
0.5
2.3
0.4
UNIT
MAX
0.2
ns
ns
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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Analog Switch Characteristics
TA = 25C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response
(switch ON)
(1)
COM or Y
Y or COM
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
(2)
Crosstalk
(between switches)
COM or Y
Y or COM
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
Crosstalk
(control input to signal output)
INH
COM or Y
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square
wave)
(see Figure 8)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
Feed-through attenuation
(switch OFF)
(3)
COM or Y
Y or COM
CL = 5 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
(1)
(2)
(3)
VCC
TYP
0.8 V
90
1.1 V
101
1.4 V
110
1.65 V
122
2.3 V
198
0.8 V
>500
1.1 V
>500
1.4 V
>500
1.65 V
>500
2.3 V
>500
0.8 V
–59
1.1 V
–59
1.4 V
–59
1.65 V
–59
2.3 V
–60
0.8 V
–55
1.1 V
–55
1.4 V
–55
1.65 V
–55
2.3 V
–55
0.8 V
0.56
1.1 V
0.68
1.4 V
0.81
1.65 V
0.93
2.3 V
1.5
0.8 V
–60
1.1 V
–60
1.4 V
–60
1.65 V
–60
2.3 V
–60
0.8 V
–59
1.1 V
–59
1.4 V
–59
1.65 V
–59
2.3 V
–59
UNIT
MHz
dB
mV
dB
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
Adjust fin voltage to obtain 0 dBm at input.
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Analog Switch Characteristics (continued)
TA = 25C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
Sine-wave distortion
COM or Y
Y or COM
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 10)
VCC
TYP
0.8 V
6.19
1.1 V
0.39
1.4 V
0.06
1.65 V
0.02
2.3 V
0.01
0.8 V
3.55
1.1 V
0.38
1.4 V
0.04
1.65 V
0.02
2.3 V
0.02
UNIT
%
Operating Characteristics
for INH input, TA = 25C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
3
3
3
3
3
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
5.5
5.5
5.5
5.5
5.5
0.5
0.5
0.5
0.5
0.5
UNIT
pF
Operating Characteristics
for A input, TA = 25C
PARAMETER
Cpd
6
Power
dissipation
capacitance
Outputs
enabled
Outputs
disabled
f = 10 MHz
UNIT
pF
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PARAMETER MEASUREMENT INFORMATION
VCC
VIL or VIH
VIL
VI = VCC or GND
VCC
A
VA
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
COM
Y2
(On)
2
GND
IS
V
r on +
VI * VO
W
IS
VI - VO
Figure 1. On-State Resistance Test Circuit
120
100
VCC = 1.1 V
80
60
40
VCC = 1.65 V
20
VCC = 2.3 V
0
0
1
2
3
Figure 2. Typical ron as a Function of Voltage (VI) for VI = 0 to VCC
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PARAMETER MEASUREMENT INFORMATION
VCC
A
VIL or VIH
VA
INH
VIH
S
VA
1
VIL
2
VIH
1
Y1
S
VINH
VO
COM
A
VI
VCC
Y2
(Off)
2
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VA
INH
VIL
VI
VCC
A
VIL or VIH
Y1
VA
1
VIL
2
VIH
1
S
VINH
A
S
VO
COM
Y2
2
VO = Open
VI = VCC or GND
(On)
GND
Figure 4. On-State Switch Leakage-Current Test Circuit
8
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PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
INPUTS
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
VI
tr/tf
VCC
VCC
VCC
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
VCC
VIL or VIH
VIL
0.1 µF
VCC
A
VA
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
COM
Y2
2
RL
fin
(On)
50 Ω
CL
GND
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
Figure 6. Frequency Response (Switch On)
VIL or VIH
A
VCC
VA
TEST CONDITION
VIL
20log10(VO2/VI)
VCC
VIH
20log10(VO1/VI)
VA
Y1
VIL
0.1 µF
INH
VO1
RL
600 Ω
VINH
CL
50 pF
COM
VCC/2
Rin
600 Ω
fin
50 Ω
Y2
VO2
GND
RL
600 Ω
CL
50 pF
VCC/2
Figure 7. Crosstalk (Between Switches)
10
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PARAMETER MEASUREMENT INFORMATION
VCC
VCC
A
VIL or VIH
VA
INH
Y1
S
VA
1
VIL
2
VIH
1
S
VINH
VO
Y2
50 Ω
COM
(On)
2
RL
600 Ω
CL
50 pF
GND
VCC/2
Rin
600 Ω
VCC/2
Figure 8. Crosstalk (Control Input, Switch Output)
VCC
VCC
A
VIL or VIH
S
VA
1
VIL
2
VIH
VA
INH
VIL
Y1
1
S
VINH
0.1 µF
VO
COM
Y2
2
RL
fin
50 Ω
RL
(Off)
CL
GND
VCC/2
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
VCC/2
Figure 9. Feedthrough (Switch Off)
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PARAMETER MEASUREMENT INFORMATION
VCC
VIL or VIH
VIL
10 µF
VCC
A
VA
INH
Y1
600 Ω
VA
1
VIL
2
VIH
1
10 µF
S
VINH
VO
COM
fin
S
Y2
(On)
2
RL
10 kΩ
CL
50 pF
GND
VCC/2
VCC = 0.8 V, VI = 0.7 VP-P
VCC = 1.1 V, VI = 1 VP-P
VCC = 1.4 V, VI = 1.2 VP-P
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
Figure 10. Sine-Wave Distortion
12
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PACKAGE OPTION ADDENDUM
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6-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AUC2G53DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U53
Z
SN74AUC2G53DCTRE4
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U53
Z
SN74AUC2G53DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(U53Q, U53R)
SN74AUC2G53DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U53R
SN74AUC2G53YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
U4N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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