SN74AUCH32244ZKER

SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 D D D D D D Member of the Texas Instruments Widebus+ Family Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.8 ns at 1.8 V Low Power Consumption, 40-µA Max ICC D D D D ±8-mA Output Drive at 1.8 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 32-bit buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUCH32244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C LFBGA – GKE Tape and reel SN74AUCH32244GKER MK244 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 terminal assignments 1 2 3 4 5 6 A A 1Y2 1Y1 1OE 2OE 1A1 1A2 B B 1Y4 1Y3 GND GND 1A3 1A4 C C 2Y2 2Y1 2A2 D 2Y4 2Y3 VCC GND 2A1 D VCC GND 2A3 2A4 E 3Y2 3Y1 GND GND 3A1 3A2 F 3Y4 3Y3 3A4 4Y2 4Y1 VCC GND 3A3 G VCC GND 4A1 4A2 H 4Y3 4Y4 4OE 3OE 4A4 4A3 E F G H J K J 5Y2 5Y1 5OE 6OE 5A1 5A2 K 5Y4 5Y3 GND GND 5A3 5A4 L 6Y2 6Y1 VCC GND 6A1 6A2 M 6Y4 6Y3 VCC GND 6A3 6A4 M N 7Y2 7Y1 GND GND 7A1 7A2 N P 7Y4 7Y3 7A4 R 8Y2 8Y1 VCC GND 7A3 P VCC GND 8A1 8A2 R T 8Y3 8Y4 8OE 7OE 8A4 8A3 L T FUNCTION TABLE (each 4-bit buffer) INPUTS 2 OE A OUTPUT Y L H H L L L H X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 5OE 5A1 5A2 5A3 5A4 6OE 6A1 6A2 6A3 6A4 A3 3OE A5 A2 A6 A1 B5 B2 B6 B1 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 A4 4OE C5 C2 C6 C1 D5 D2 D6 D1 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 J3 7OE J5 J2 J6 J1 K5 K2 K6 K1 5Y1 7A1 5Y2 7A2 5Y3 7A3 5Y4 7A4 J4 8OE L5 L2 L6 L1 M5 M2 M6 M1 6Y1 8A1 6Y2 8A2 6Y3 8A3 6Y4 8A4 POST OFFICE BOX 655303 H4 E5 E2 E6 E1 F5 F2 F6 F1 3Y1 3Y2 3Y3 3Y4 H3 G5 G2 G6 G1 H6 H1 H5 H2 4Y1 4Y2 4Y3 4Y4 T4 N5 N2 N6 N1 P5 P2 P6 P1 7Y1 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 T5 T2 • DALLAS, TEXAS 75265 8Y1 8Y2 8Y3 8Y4 3 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 0.8 V VCC = 1.1 V to 1.95 V High-level input voltage VCC = 2.3 V to 2.7 V VCC = 0.8 V VIL Low-level input voltage VI Input voltage VO ∆t/∆v 0.8 2.7 VCC 0.65 × VCC Output voltage High-level output current V 1.7 0 0.35 × VCC V 0.7 3.6 V 0 3-state 0 VCC 3.6 V –0.7 –3 –5 mA –8 –9 0.7 VCC = 1.1 V VCC = 1.4 V 3 VCC = 1.65 V VCC = 2.3 V 8 VCC = 0.8 V VCC = 1.3 V VCC = 1.6 V, 1.95 V, and 2.7 V Input transition rise or fall rate V Active state VCC = 1.4 V VCC = 1.65 V Low-level output current UNIT 0 VCC = 2.3 V VCC = 0.8 V IOL MAX VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 0.8 V VCC = 1.1 V IOH MIN 5 mA 9 20 15 ns/V 10 TA Operating free-air temperature –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 0.8 V to 2.7 V IOH = –100 µA IOH = –0.7 mA VOH VOL II IBHL‡ IBHH§ IBHLO¶ A or OE inputs MIN TYP† MAX 0.8 V 0.55 IOH = –3 mA IOH = –5 mA 1.1 V 0.8 1.4 V 1 IOH = –8 mA IOH = –9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.2 0.8 V 0.25 IOL = 3 mA IOL = 5 mA 1.1 V 0.3 1.4 V 0.4 IOL = 8 mA IOL = 9 mA 1.65 V 0.45 2.3 V 0.6 VI = VCC or GND VI = 0.35 V ±5 0 to 2.7 V VI = 0.47 V VI = 0.57 V 1.1 V 10 1.4 V 15 1.65 V 20 VI = 0.7 V VI = 0.8 V 2.3 V 40 1.1 V –10 VI = 0.9 V VI = 1.07 V 1.4 V –15 1.65 V –20 VI = 1.7 V 2.3 V –40 VI = 0 to VCC IBHHO# VI = 0 to VCC Ioff IOZ VI or VO = 2.7 V VO = VCC or GND ICC Ci VI = VCC or GND, VI = VCC or GND IO = 0 UNIT VCC–0.1 1.3 V 75 1.6 V 125 1.95 V 175 2.7 V 275 1.3 V –75 1.6 V –125 1.95 V –175 2.7 V –275 V µA µA µA µA µA 0 ±10 µA 2.7 V ±10 µA 40 µA 4.5 pF 0.8 V to 2.7 V 2.5 V 3 Co VO = VCC or GND 2.5 V 4 7 pF † All typical values are at TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX tpd A Y 5.4 0.8 2.8 0.6 1.9 0.7 1.3 1.8 0.5 1.8 ns ten OE Y 8 1 4.4 0.7 2.6 0.8 1.4 2.5 0.6 1.9 ns tdis OE Y 12 1.9 4.9 1 4.6 1.5 2.6 4 0.5 2 ns PARAMETER UNIT operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS VCC = 0.8 V TYP 21 VCC = 1.2 V TYP VCC = 1.5 V TYP 22 23 VCC = 1.8 V TYP 25 VCC = 2.5 V TYP UNIT 30 f = 10 MHz pF 1 POST OFFICE BOX 655303 1 • DALLAS, TEXAS 75265 1 1 1 SN74AUCH32244 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES412B – SEPTEMBER 2002 – REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT CL RL 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input th VCC VCC/2 VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input 0V tPHL tPLH VCC/2 VOL tPHL VOH Output tPLZ VCC VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH VCC/2 VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC/2 tPZL VOH VCC/2 Output VCC Output Control VCC/2 VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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