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SN74AUP1G34
SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
SN74AUP1G34 Low-Power Single Buffer Gate
1 Features
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2 Applications
2
Available in the Ultra Small 0.64 mm Package
(DPW) with 0.5-mm Pitch
Low Static-Power Consumption;
ICC = 0.9 μA Max
Low Dynamic-Power Consumption;
Cpd = 4.1 pF Typ at 3.3 V
Low Input Capacitance; Ci = 1.5 pF Typ
Low Noise - Overshoot and Undershoot <
10% of VCC
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 4.1 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
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ATCA Solutions
Active Noise Cancellation (ANC)
Barcode Scanner
Blood Pressure Monitor
CPAP Machine
Cable Solutions
DLP 3D Machine Vision, Hyperspectral Imaging,
Optical Networking, and Spectroscopy
E-Book
Embedded PC
Field Transmitter: Temperature or Pressure
Sensor
Fingerprint Biometrics
HVAC: Heating, Ventilating, and Air Conditioning
Network-Attached Storage (NAS)
Server Motherboard and PSU
Software Defined Radio (SDR)
TV: High-Definition (HDTV), LCD, and Digital
Video Communications System
Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
X-ray: Baggage Scanner, Medical, and Dental
3 Description
This single buffer gate performs the Boolean function
Y = A in positive logic.
Device Information(1)
PART NUMBER
SN74AUP1G34
PACKAGE
BODY SIZE (NOM)
SOT (5)
1.60 mm × 1.20 mm
USON (6)
1.45 mm × 1.00 mm
X2SON (4)
0.80 mm × 0.80 mm
DSBGA (4)
0.79 mm × 0.79 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplifed Schematic
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G34
SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplifed Schematic..............................................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
3
4
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 5 pF ........................
Switching Characteristics, CL = 10 pF ......................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, CL = 30 pF ......................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
8.1 Propagation Delays, Setup and Hold Times, and
8.2
9
Pulse Width................................................................ 8
Enable and Disable Times ....................................... 9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1 Trademarks ........................................................... 13
13.2 Electrostatic Discharge Caution ............................ 13
13.3 Glossary ................................................................ 13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision J (June 2014) to Revision K
•
Page
Updated Device Information table. ........................................................................................................................................ 1
Changes from Revision I (November 2012) to Revision J
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ...................................................................................................................................... 1
•
Updated Description. ............................................................................................................................................................. 1
•
Added Device Information table. ........................................................................................................................................... 1
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Added Handling Ratings table. ............................................................................................................................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 4
•
Added Typical Characteristics. ............................................................................................................................................... 7
Changes from Revision H (October 2012) to Revision I
•
2
Page
Changed DPW package pinout .............................................................................................................................................. 3
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SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
6 Pin Configuration and Function
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
N.C.
N.C.
5
1
A
2
2
GND
3
GND
4
6
YFP PACKAGE
(TOP VIEW)
YZP PACKAGE
(TOP VIEW)
VCC
A
2
5
N.C.
GND
3
4
Y
4
Y
1
6
A
2
5
N.C.
GND
3
4
Y
Y
DSF PACKAGE
(TOP VIEW)
1
3
VCC
N.C.
Y
4
3
VCC
2
GND
A
5
1
VCC
A
N.C.
VCC N.C.
5
1
DRY PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
N.C.
A
GND
A1
1
B1
2
C1
3
VCC
5 A2
A
GND
A1
1
4 A2
B1
2
3
B2
VCC
Y
DPW PACKAGE
(TOP VIEW)
N.C.
GND
A
1
5
3
2
4
VCC
Y
Y
4 C2
N.C. – No internal connection
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
DBV,
DCK,
DRL
DSF,
DRY
NC
1
A
2
GNY
Y
VCC
YFP
DPW
YFP
1, 5
–
1
2
A1
2
A1
3
3
B1
3
4
4
B2
4
5
6
A2
5
I/O
DESCRIPTION
–
No connect
I
Input A
B1
–
Ground
B2
O
Output Y
A2
–
Power Pin
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
UNIT
V
(2)
VI
Input voltage range
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
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7.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
MAX
0.8
3.6
VCC = 2.3 V to 2.7 V
V
1.6
2
VCC = 0.8 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
(2)
High-level output current
0.9
0
3.6
0
(2)
Low-level output current
VCC
V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
mA
-4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
V
VCC = 0.8 V
VCC = 3 V
IOL
V
0.7
VCC = 3 V to 3.6 V
IOH
V
0.65 × VCC
VCC = 3 V to 3.6 V
VIL
UNIT
VCC
VCC = 1.1 V to 1.95 V
High-level input voltage
MIN
µA
mA
4
VCC = 0.8 V to 3.6 V
200
ns/V
85
°C
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Defined by the signal integrity requirements and design goal priorities
7.4 Thermal Information
THERMAL METRIC (1)
DBV
DCK
DRL
DSF
DRY
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
271.4
338.4
349.7
407.1
554.9
RθJC(top)
Junction-to-case (top) thermal resistance
213.5
110.6
120.5
232.0
385.4
RθJB
Junction-to-board thermal resistance
108.2
118.8
171.4
306.9
388.2
ψJT
Junction-to-top characterization parameter
89.3
3.0
10.8
40.3
159.0
ψJB
Junction-to-board characterization parameter
107.6
117.8
169.4
306.0
384.1
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
TA = 25°C
VCC
MIN
TYP
MAX
MIN
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
IOH = –2.3 mA
2.3 V
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
TA = –40°C to 85°C
2.6
IOL = 20 µA
0.8 V to 3.6 V
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
MAX
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
IOL = 2.3 mA
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
3V
IOL = 4 mA
UNIT
V
0 V to 3.6 V
0.1
0.5
μA
Ioff
VI or VO = 0 V to
3.6 V
0V
0.2
0.6
μA
ΔIoff
VI or VO = 0 V to
3.6 V
0 V to 0.2 V
0.2
0.6
μA
ICC
VI = GND or
(VCC to 3.6 V)
IO = 0
0.8 V to 3.6 V
0.5
0.9
μA
ΔICC
VI = VCC – 0.6 V
IO = 0
3.3 V
40
50
μA
II
A input
VI = GND to 3.6 V
Ci
VI = VCC or GND
Co
VO = GND
0V
1.5
3.6 V
1.5
0V
2.5
pF
pF
7.6 Switching Characteristics, CL = 5 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
0.8 V
tpd
A
Y
TA = 25°C
MIN
TA = –40°C to 85°C
TYP MAX
MIN
MAX
1.8
14.5
27.4
1.2 V ± 0.1 V
3
5.6
11.2
0.4
13.9
1.5 V ± 0.1 V
2.5
4
7.2
0.7
9.2
1.8 V ± 0.15 V
2.2
3.2
6
0.8
7.3
2.5 V ± 0.2 V
1.8
2.4
3.9
0.6
5.1
3.3 V ± 0.3 V
1.4
2
3.2
0.6
4.1
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UNIT
ns
5
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SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
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7.7 Switching Characteristics, CL = 10 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC
TA = 25°C
MIN
TA = –40°C to 85°C
TYP MAX
MIN
MAX
0.8 V
2.7
16.6
28.2
1.2 V ± 0.1 V
3.6
6.6
12.7
0.3
15.4
1.5 V ± 0.1 V
3
4.8
8.3
1.2
10.3
1.8 V ± 0.15 V
2.7
3.9
6.9
1.3
8.3
2.5 V ± 0.2 V
2.3
2.9
4.5
1.2
5.8
3.3 V ± 0.3 V
2
2.4
3.8
1.1
4.8
UNIT
ns
7.8 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC
TA = 25°C
TA = –40°C to 85°C
MIN
TYP
MAX
MIN
MAX
0.8 V
5.1
18.6
30.2
1.2 V ± 0.1 V
4.3
7.5
1.5 V ± 0.1 V
3.6
5.5
13.6
1.3
16.5
9
1.9
1.8 V ± 0.15 V
3.2
11.2
4.5
7.5
1.9
8.9
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.6
3.4
5.2
1.7
6.5
2.3
2.9
4.2
1.5
5
UNIT
ns
7.9 Switching Characteristics, CL = 30 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC
TA = 25°C
TA = –40°C to 85°C
MIN
TYP
MAX
MIN
MAX
18.9
0.8 V
9.9
24.2
36.3
1.2 V ± 0.1 V
6.3
10.1
16.3
3.6
1.5 V ± 0.1 V
5.1
7.4
11
3.4
13
1.8 V ± 0.15 V
4.5
6.1
9.3
3.2
10.6
2.5 V ± 0.2 V
3.7
4.7
6.4
2.7
7.8
3.3 V ± 0.3 V
3.3
4
5.3
2.5
6.5
UNIT
ns
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC
TYP
0.8 V
3.8
1.2 V ± 0.1 V
3.8
1.5 V ± 0.1 V
3.8
1.8 V ± 0.15 V
3.8
2.5 V ± 0.2 V
3.9
3.3 V ± 0.3 V
4.1
UNIT
pF
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7.11 Typical Characteristics
20
6
TPD in ns
TPD in ns
5
15
TPD (ns)
TPD (ns)
4
10
3
2
5
1
0
0
1
2
3
4
VCC (V)
0
-50
0
D001
Figure 1. TPD vs VCC 15 pF Load
50
Temperature (°C)
100
150
D001
Figure 2. TPD vs Temperature 15 pF Load
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8 Parameter Measurement Information
8.1 Propagation Delays, Setup and Hold Times, and Pulse Width
From Output
Under Test
CL
(see Note A)
1 MW
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
Output
VM
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR £ 10 Mhz, ZO = 50 W, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8.2
SCES603K – AUGUST 2004 – REVISED OCTOBER 2014
Enable and Disable Times
2 ´ VCC
5 kW
From Output
Under Test
CL
(see Note A)
S1
GND
5 kW
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 ´ VCC
GND
LOAD CIRCUIT
VCC = 0.8 V
CL
VM
VI
VD
VCC = 1.2 V
± 0.1 V
5, 10, 15, 30 pF 5, 10, 15, 30 pF
VCC/2
VCC/2
VCC
VCC
0.1 V
0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 ´ VCC
(see Note B)
VCC = 1.5 V
± 0.1 V
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + VD
VOL
tPHZ
VCC/2
VOH - VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
This single buffer gate operates from 0.8 V to 3.6 V and performs the Boolean function Y = A in positive logic.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW
package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square
footprint saves significant board space over other package options while still retaining the traditional
manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current back-flow through the device when it is powered. The Ioff feature also allows for live
insertion.
9.2 Functional Block Diagram
A
Y
9.3 Feature Description
•
•
•
•
•
Wide operating VCC range of 0.8 V to 3.6 V
3.6-V I/O tolerant to support down translation
Input hysteresis allows slow input transition and better switching noise immunity at the input
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
Low noise due to slower edge rates
9.4 Device Functional Modes
Table 1. Function Table
10
INPUT
A
OUTPUT
Y
H
H
L
L
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10 Application and Implementation
10.1 Application Information
The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It
has a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive produces
slower edges and prevents overshoot and undershoot on the outputs.
The AUP family of single gate logic makes excellent translators for the new lower voltage Micro- processors that
typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that
are still powered by 3.3 V to the new uC power levels.
10.2 Typical Application
3.3-V Bus driver
VCC
1 V regulated
0.1 µF
1-V Micro Processor
µC
Driver
Figure 5. Typical Application
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits.
10.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specifications. See (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 20 mA on the output and 50 mA total for the part
– Outputs should not be pulled above VCC
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SN74AUP1G34
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Typical Application (continued)
10.2.3 Application Curves
Switching Characteristics
at 25 MHz†
3.5
Voltage − V
3
2.5
Input
2
1.5
1
Output
0.5
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 7. Excellent Signal Integrity
Figure 6. AUP – The Lowest-Power Family
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended and if there are multiple VCC terminals then .01 μF or .022 μF is recommended
for each power terminal. It is ok to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal
as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC whichever make more sense or is more convenient. It is generally OK to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when
asserted. This will not disable the input section of the I.O’s so they also cannot float when disabled.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
12
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13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AUP1G34DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H34R
SN74AUP1G34DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
H34R
SN74AUP1G34DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(H95, H9F, H9K, H9
R)
SN74AUP1G34DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(H95, H9R)
SN74AUP1G34DPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
G4
SN74AUP1G34DRLR
ACTIVE
SOT-5X3
DRL
5
4000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(H97, H9R)
SN74AUP1G34DRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
H9
SN74AUP1G34DSFR
ACTIVE
SON
DSF
6
5000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
H9
SN74AUP1G34YFPR
ACTIVE
DSBGA
YFP
4
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
H9
N
SN74AUP1G34YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
H9N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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