SN74BCT2240DW

SN54BCT2240, SN74BCT2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS030E − SEPTEMBER 1988 − REVISED MARCH 2003 D Operating Voltage Range of 4.5 V to 5.5 V D State-of-the-Art BiCMOS Design SN54BCT2240 . . . J OR W PACKAGE SN74BCT2240 . . . DB, DW, N,OR NS PACKAGE (TOP VIEW) Significantly Reduces ICCZ D Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN74BCT2241 and the ’BCT2244 devices, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. These devices feature high fan-out and improved fan-in. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 2Y4 1A1 1OE VCC SN54BCT2240 . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 The ’BCT2240 devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 2OE D 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The outputs, which are designed to source or sink up to 12 mA, include 33-Ω series resistors to reduce overshoot and undershoot. ORDERING INFORMATION PDIP − N 0°C 0 C to 70°C 70 C −55°C to 125°C † ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube SN74BCT2240N Tube SN74BCT2240DW Tape and reel SN74BCT2240DWR SOP − NS Tape and reel SN74BCT2240NSR BCT2240 SSOP − DB Tape and reel SN74BCT2240DBR BA240 CDIP − J Tube SNJ54BCT2240J SNJ54BCT2240J CFP − W Tube SNJ54BCT2240W SNJ54BCT2240W LCCC − FK Tube SNJ54BCT2240FK SNJ54BCT2240FK SOIC − DW SN74BCT2240N BCT2240 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SN54BCT2240, SN74BCT2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS030E − SEPTEMBER 1988 − REVISED MARCH 2003 FUNCTION TABLE (each buffer) INPUTS OUTPUT Y OE A L H L L L H H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 2 1 2 18 4 16 6 14 8 12 1Y1 1Y2 1Y3 1Y4 19 11 9 13 7 15 5 17 3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2Y1 2Y2 2Y3 2Y4 SN54BCT2240, SN74BCT2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS030E − SEPTEMBER 1988 − REVISED MARCH 2003 schematic of Y outputs VCC Output GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Input clamp current, IIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SN54BCT2240, SN74BCT2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS030E − SEPTEMBER 1988 − REVISED MARCH 2003 recommended operating conditions (see Note 3) SN54BCT2240 SN74BCT2240 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 V IIK Input clamp current −18 −18 mA IOH High-level output current −12 −12 mA IOL Low-level output current 12 mA TA Operating free-air temperature 70 °C 2 2 V 12 −55 125 V 0 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54BCT2240 PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, MIN TYP† 2.4 2 SN74BCT2240 MIN TYP† 3.3 2.4 3.3 3.2 2 3.2 II = −18 mA MAX −1.2 IOH = −1 mA MAX −1.2 UNIT V VOH VCC = 4 4.5 5V VOL VCC = 4 4.5 5V II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 μA IIL VCC = 5.5 V, VI = 0.5 V −1 −1 mA IOZH VCC = 5.5 V, VO = 2.7 V 50 50 μA IOZL VCC = 5.5 V, VO = 0.5 V ‡ VCC = 5.5 V, VO = 0 ICCH VCC = 5.5 V, Outputs open 19 32 ICCL VCC = 5.5 V, Outputs open 46 76 ICCZ VCC = 5.5 V, Outputs open 6 8 IOS IOH = −12 mA V IOL = 1 mA 0.15 0.5 0.15 0.5 IOL = 12 mA 0.35 0.8 0.35 0.8 −50 μA −225 mA 19 32 mA 46 76 mA 6 8 mA −50 −100 −225 V −100 † All typical values are at VCC = 5 V, TA = 25°C. † Not more than one output should be tested at a time, and the duration of the test should not exceed one second. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL =50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ 4 FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 5 V, TA = 25°C • SN54BCT2240 MIN TYP MAX MIN MAX MIN MAX 0.5 3.4 4.8 0.5 6.3 0.5 5.7 0.5 2.8 4 0.5 4.6 0.5 4.4 2.6 6.2 8.2 2.6 10.1 2.6 9.3 4.3 8.8 10.9 4.3 12.9 4.3 12.4 2 5.3 7.1 2 9.2 2 8.7 2.2 6.7 8.5 2.2 12.2 2.2 10.6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN74BCT2240 UNIT ns ns ns SN54BCT2240, SN74BCT2240 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS SCBS030E − SEPTEMBER 1988 − REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse (see Note B) 3V Timing Input (see Note B) 3V 1.5 V 1.5 V 0V 1.5 V tw 0V Data Input (see Note B) 3V th tsu Low-Level Pulse 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enable) 3V Input (see Note B) 1.5 V 1.5 V 0V In-Phase Output (see Note D) VOH 1.5 V VOL 0V 1.5 V 3.5 V VOL tPHZ VOH 1.5 V tPLZ 1.5 V Waveform 1 (see Notes C and D) tPLH tPHL Out-of-Phase Output (see Note D) 1.5 V 1.5 V tPZL tPHL tPLH 1.5 V 0.3 V tPZH Waveform 2 (see Notes C and D) VOL VOH 1.5 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open. F. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9093901M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629093901M2A SNJ54BCT 2240FK 5962-9093901MRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9093901MR A SNJ54BCT2240J SN74BCT2240DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI 0 to 70 SNJ54BCT2240FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629093901M2A SNJ54BCT 2240FK SNJ54BCT2240J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9093901MR A SNJ54BCT2240J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN54BCT2240, SN74BCT2240 : • Catalog: SN74BCT2240 • Military: SN54BCT2240 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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