SN74BCT373DWR

SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 D D Operating Voltage Range of 4.5 V to 5.5 V State-of-the-Art BiCMOS Design Significantly Reduces ICCZ Full Parallel Access for Loading D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) SN54BCT373 . . . J OR W PACKAGE SN74BCT373 . . . DB, DW, N, OR NS PACKAGE (TOP VIEW) 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1D 1Q OE VCC 1 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND LE 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND SN54BCT373 . . . FK PACKAGE (TOP VIEW) 8Q D D description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION PDIP – N 0°C to 70°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube SN74BCT373N Tube SN74BCT373DW Tape and reel SN74BCT373DWR SOP – NS Tape and reel SN74BCT373NSR BCT373 SSOP – DB Tape and reel SN74BCT373DBR BT373 CDIP – J Tube SNJ54BCT373J SNJ54BCT373J CFP – W Tube SNJ54BCT373W SNJ54BCT373W LCCC – FK Tube SNJ54BCT373FK SOIC – DW SN74BCT373N BCT373 SNJ54BCT373FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 1D To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1Q SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Input clamp current, IIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Current into any output in the low state: SN54BCT373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74BCT373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54BCT373 SN74BCT373 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 0.8 V Input clamp current –18 –18 mA IOH IOL High-level output current –12 –15 mA Low-level output current 48 64 mA High-level input voltage 2 2 V V TA Operating free-air temperature –55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54BCT373 TYP† MAX TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V MIN II = –18 mA IOH = –3 mA –1.2 IOH = –12 mA IOH = –15 mA VOL VCC = 4 4.5 5V IOL = 48 mA IOL = 64 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V VI = 2.7 V IIL IOS‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 0 IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V ICCL ICCH VCC = 5.5 V VCC = 5.5 V ICCZ Ci VCC = 5.5 V VCC = 5 V, SN74BCT373 TYP† MAX MIN 2.4 3.3 2 3.2 –1.2 2.4 3.1 0.55 0.42 0.55 V 0.4 0.4 mA 20 20 µA –0.6 –100 V 3.3 V 2 0.38 UNIT –225 –100 50 –0.6 mA –225 mA 50 µA –50 µA 37 60 37 60 mA 2 5 2 5 mA 5 8 5 8 mA –50 VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 6 Co VCC = 5 V, 11 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 6 pF 11 pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C MIN tw tsu Pulse duration, LE high th Hold time, data after LE↓ 4 Setup time, data before LE↓ POST OFFICE BOX 655303 MAX SN54BCT373 MIN MAX SN74BCT373 MIN UNIT MAX 7.5 7.5 7.5 ns 2 2 2 ns 5.5 5.5 5.5 ns • DALLAS, TEXAS 75265 SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX† ’BCT373 tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q SN54BCT373 UNIT SN74BCT373 MIN TYP MAX MIN MAX MIN MAX 2 5.9 7.7 1.5 10.1 2 9.3 2 6.7 8.5 1 10.3 1.5 9.5 2 6.2 8.2 2 10.1 2 9.3 2 5.9 7.8 2 9.2 2 8.8 1 7.8 9.6 1 12.3 1 11.8 1 8.2 10.2 1 12.5 1 12 1 4.9 6.6 1 7.4 1 7 1 5 6.7 1 8.1 1 7.4 ns ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54BCT373, SN74BCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse (see Note B) 3V Timing Input (see Note B) 3V 1.5 V 1.5 V 0V 1.5 V tw 0V Data Input (see Note B) 3V th tsu Low-Level Pulse 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enable) 3V Input (see Note B) 1.5 V 1.5 V 0V tPLH In-Phase Output (see Note D) 1.5 V VOL VOH 1.5 V 1.5 V 0V tPLZ 1.5 V Waveform 1 (see Notes C and D) 3.5 V VOL tPHZ tPLH tPHL Out-of-Phase Output (see Note D) 1.5 V 1.5 V tPZL tPHL VOH 1.5 V 0.3 V tPZH Waveform 2 (see Notes C and D) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) VOH 1.5 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open. F. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) 5962-9074601M2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629074601M2A SNJ54BCT 373FK 5962-9074601MRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9074601MR A SNJ54BCT373J SNJ54BCT373FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629074601M2A SNJ54BCT 373FK SNJ54BCT373J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9074601MR A SNJ54BCT373J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of