SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
D Operating Voltage Range of 4.5 V to 5.5 V
D State-of-the-Art BiCMOS Design
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
Significantly Reduces ICCZ
D Full Parallel Access for Loading
SN54BCT573 . . . J OR W PACKAGE
SN74BCT573 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3D
4D
5D
6D
7D
1Q
20
2
2D
1D
OE
VCC
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
SN54BCT573 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched
at the logic levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
PDIP − N
0°C to 70°C
−55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74BCT573N
Tube
SN74BCT573DW
Tape and reel
SN74BCT573DWR
SOP − NS
Tape and reel
SN74BCT573NSR
BCT573
CDIP − J
Tube
SNJ54BCT573J
SNJ54BCT573J
CFP − W
Tube
SNJ54BCT573W
SNJ54BCT573W
LCCC − FK
Tube
SNJ54BCT573FK
SNJ54BCT573FK
SOIC − DW
SN74BCT573N
BCT573
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
1
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA
Current into any output in the low state: SN54BCT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54BCT573
SN74BCT573
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
−18
−18
mA
IOH
High-level output current
−12
−15
mA
IOL
Low-level output current
64
mA
TA
Operating free-air temperature
70
°C
2
2
V
48
−55
125
V
0
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT573
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V
TYP†
2.4
3.3
2
3.2
II = −18 mA
SN74BCT573
MAX
MIN
TYP†
2.4
3.3
2
3.1
−1.2
IOH = −3 mA
VOH
MIN
IOH = −12 mA
0.38
−1.2
UNIT
V
V
IOH = −15 mA
IOL = 48 mA
MAX
0.55
VOL
VCC = 4
4.5
5V
II
VCC = 5.5 V,
VI = 5.5 V
0.4
0.4
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
μA
IIL
VCC = 5.5 V,
VI = 0.5 V
IOS‡
VCC = 5.5 V,
VO = 0
IOZH
VCC = 5.5 V,
VO = 2.7 V
IOZL
VCC = 5.5 V,
VO = 0.5 V
ICCL
VCC = 5.5 V,
Outputs open
ICCH
VCC = 5.5 V,
ICCZ
VCC = 5.5 V,
Ci
VCC = 5 V,
VI = 2.5 V or 0.5 V
5.5
5.5
pF
Co
VCC = 5 V,
VO = 2.5 V or 0.5 V
7.5
7.5
pF
IOL = 64 mA
0.42
−0.6
0.55
V
−0.6
mA
−225
mA
50
50
μA
−50
−50
μA
62
62
mA
Outputs open
8
8
mA
Outputs open
8
8
mA
−100
−225
−100
†
All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
MAX
SN54BCT573
MIN
MAX
SN74BCT573
MIN
UNIT
MAX
tw
Pulse duration, LE high
4
4
4
ns
tsu
Setup time, data before LE↓
1
2.5
1
ns
th
Hold time, data after LE↓
4
4
4
ns
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
4
FROM
(INPUT)
TO
(OUTPUT)
D
Q
LE
Q
OE
Q
OE
Q
VCC = 5 V,
TA = 25°C
•
SN54BCT573
MIN
TYP
MAX
MIN
MAX
MIN
MAX
2
5
7.2
1
9.8
2
8.4
2.8
5.9
8.2
1.5
10.3
2.8
9.6
2.4
6.1
7.2
2
9.7
2.4
8.1
2.9
5.2
7.1
2
8.8
2.9
7.8
3
6.2
8.5
2.5
11
3
10.4
4.3
7.1
9.3
3.5
11.5
4.3
11
2.2
3.9
5.6
1.5
7.2
2.2
6
1.7
3.6
5.2
1
7
1.7
6
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SN74BCT573
UNIT
ns
ns
ns
ns
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
S1
Open
(all others)
From Output
Under Test
Test
Point
CL
(see Note A)
R1
From Output
Under Test
R1
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
RL = R1 = R2
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
Timing Input
(see Note B)
3V
1.5 V
1.5 V
0V
1.5 V
tw
0V
Data Input
(see Note B)
3V
th
tsu
Low-Level
Pulse
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Output
Control
(low-level enable)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
In-Phase
Output
(see Note D)
VOH
1.5 V
VOL
0V
1.5 V
3.5 V
VOL
tPHZ
VOH
1.5 V
tPLZ
1.5 V
Waveform 1
(see Notes C and D)
tPLH
tPHL
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
tPZL
tPHL
tPLH
1.5 V
0.3 V
tPZH
Waveform 2
(see Notes C and D)
VOL
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74BCT573DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
BCT573
SN74BCT573N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74BCT573N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of