SN74BCT8245ANT

SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 D Members of the Texas Instruments D D D D D SCOPE ™ Family of Testability Products Octal Test-Integrated Circuits Functionally Equivalent to ’F245 and ’BCT245 in the Normal- Function Mode Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Test Operation Synchronous to Test Access Port (TAP) Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V ) on TMS Pin SCOPE ™ Instruction Set − IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ − Parallel-Signature Analysis at Inputs − Pseudo-Random Pattern Generation From Outputs − Sample Inputs/Toggle Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT) DIR B1 B2 B3 B4 GND B5 B6 B7 B8 TDO TMS 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 OE A1 A2 A3 A4 A5 VCC A6 A7 A8 TDI TCK SN54BCT8245A . . . FK PACKAGE (TOP VIEW) A3 A4 A5 NC VCC A6 A7 D D SN54BCT8245A . . . JT PACKAGE SN74BCT8245A . . . DW OR NT PACKAGE (TOP VIEW) A2 A1 OE NC DIR B1 B2 description 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 A8 TDI TCK NC TMS TDO B8 B3 B4 GND NC B5 B6 B7 The ’BCT8245A scan test devices with octal bus transceivers are members of the Texas Instruments SCOPE™ testability integratedcircuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. 5 NC − No internal connection In the normal mode, these devices are functionally equivalent to the ’F245 and ’BCT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE™ octal bus transceivers. In the test mode, the normal operation of the SCOPE™ octal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE is a trademark of Texas Instruments Incorporated. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 description (continued) Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54BCT8245A is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74BCT8245A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (normal mode) INPUTS OE OPERATION DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† TDI TMS TCK 14 12 13 Φ SCAN ’BCT8245A TDI TMS TDO 11 TDO TCK-IN TCK-OUT OE DIR 24 1 G3 3 EN1 [BA] 3 EN2 [AB] A1 A2 A3 A4 A5 A6 A7 A8 23 2 1 1 2 22 21 4 20 5 19 7 17 8 16 9 15 10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. 2 3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • B1 B2 B3 B4 B5 B6 B7 B8 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 functional block diagram Boundary-Scan Register VCC OE 24 VCC DIR 1 VCC A1 VCC 23 2 B1 One of Eight Channels Bypass Register Boundary- Control Register VCC TDI 14 VCC 11 TDO Instruction Register VCC TMS 12 VCC TCK 13 TAP Controller Pin numbers shown are for the DW, JT, and NT packages. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 Terminal Functions 4 TERMINAL NAME DESCRIPTION A1−A8 A-bus I/O ports. See function table for normal-mode logic. Internal pullups force these I/O ports to a high level if left unconnected. B1−B8 B-bus I/O ports. See function table for normal-mode logic. Internal pullups force these I/O ports to a high level if left unconnected. DIR Normal-function direction-control input. See function table for normal-mode logic. An internal pullup forces DIR to a high level if left unconnected. GND Ground OE Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level if left unconnected. TCK Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces TCK to a high level if left unconnected. TDI Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. TDO Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active and is not driven from an external source. TMS Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (VIHH), at TMS. VCC Supply voltage • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 test architecture Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register. Test-Logic-Reset TMS = H TMS = L TMS = H TMS = H TMS = H Run-Test/Idle Select-DR-Scan Select-IR-Scan TMS = L TMS = L TMS = L TMS = H TMS = H Capture-DR Capture-IR TMS = L TMS = L Shift-DR Shift-IR TMS = L TMS = L TMS = H TMS = H TMS = H TMS = H Exit1-DR Exit1-IR TMS = L TMS = L Pause-DR Pause-IR TMS = L TMS = L TMS = H TMS = H TMS = L Exit2-DR TMS = L Exit2-IR TMS = H Update-DR TMS = H TMS = L TMS = H Update-IR TMS = H TMS = L Figure 1. TAP-Controller State Diagram • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the ’BCT8245A, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation. Run-Test/Idle The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected-data register may capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state. Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK, after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data. Update-DR If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state. Capture-IR When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’BCT8245A, the status value loaded in the Capture-IR state is the fixed binary value 10000001. Shift-IR Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register. While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state. Exit1-IR, Exit2-IR The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state. Pause-IR No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data. Update-IR The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 register overview With the exception of the bypass register, any test register may be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register. instruction register description The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. Table 2 lists the instructions supported by the ’BCT8245A. The even-parity feature specified for SCOPE™ devices is not supported in this device. Bit 7 of the instruction opcode is a don’t-care bit. Any instructions that are defined for SCOPE™ devices but are not supported by this device default to BYPASS. During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2. TDI Bit 7 (MSB) Don’t Care Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Figure 2. Instruction Register Order of Scan 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Bit 1 Bit 0 (LSB) TDO SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 data register description boundary-scan register The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function output pin. Which I/O ports, A or B, function as input terminals and which function as output terminals is determined by the DIR signal (BSC17) as described below. The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input terminals. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR may change during Run-Test/Idle, as determined by the current instruction. The contents of the BSR are not changed in Test-Logic-Reset. The BSR order of scan is from TDI through bits 17−0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. The device signals I1−I8 and O1−O8 represent data input signals and data output signals, respectively. The direction control signal (DIR) as output by BSC17 determines which port, A or B, is considered an input and which is considered an output. When the output of BSC17 is logic 0, the device signals I1−I8 are associated with I/O ports B1−B8, while device signals O1−O8 are associated with I/O ports A1−A8. When the output of BSC17 is logic 1, the converse is true (that is, I1−I8 are associated with A1−A8, while O1−O8 are associated with B1−B8). In normal-function mode, the output of the BSC17 input is equivalent to the input signal present at the DIR input pin. Table 1. Boundary-Scan Register Configuration BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL BSR BIT NUMBER DEVICE SIGNAL 17 DIR 15 I1 7 O1 16 OE 14 I2 6 O2 − − 13 I3 5 O3 − − 12 I4 4 O4 − − 11 I5 3 O5 − − 10 I6 2 O6 − − 9 I7 1 O7 − − 8 I8 0 O8 boundary-control register The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE™ instruction set. Such operations include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3. TDI Bit 1 (MSB) Bit 0 (LSB) TDO Figure 3. Boundary-Control Register Order of Scan • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4. TDI Bit 0 TDO Figure 4. Bypass Register Order of Scan instruction-register opcode description The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of each instruction. Table 2. Instruction-Register Opcodes † ‡ BINARY CODE† BIT 7 → BIT 0 MSB → LSB SCOPE OPCODE DESCRIPTION SELECTED DATA REGISTER X0000000 EXTEST/INTEST Boundary scan Boundary scan Test X0000001 BYPASS‡ Bypass scan Bypass Normal X0000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal X0000011 INTEST/EXTEST Boundary scan Boundary scan Test X0000100 BYPASS‡ Bypass scan Bypass Normal X0000101 BYPASS‡ Bypass scan Bypass Normal X0000110 HIGHZ (TRIBYP) Control boundary to high impedance Bypass Modified test MODE X0000111 CLAMP (SETBYP) Control boundary to 1/0 Bypass Test X0001000 BYPASS‡ Bypass scan Bypass Normal X0001001 RUNT Boundary run test Bypass Test X0001010 READBN Boundary read Boundary scan Normal X0001011 READBT Boundary read Boundary scan Test X0001100 CELLTST Boundary self test Boundary scan Normal X0001101 TOPHIP Boundary toggle outputs Bypass Test X0001110 SCANCN Boundary-control register scan Boundary control Normal X0001111 SCANCT Boundary-control register scan Boundary control Test All others BYPASS Bypass scan Bypass Normal Bit 7 is a don’t-care bit; X = don’t care. The BYPASS instruction is executed in lieu of a SCOPE™ instruction that is not supported in the ’BCT8245A. boundary scan This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into the output BSCs is applied to the device output terminals. The device operates in the test mode. 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device output terminals are placed in the high-impedance state, the device input terminals remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output terminals. The device operates in the test mode. boundary run test The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG). boundary read The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation. boundary self test The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode. boundary toggle outputs The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured in the input BSCs. The device operates in the test mode. boundary-control register scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 11 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 boundary-control register opcode description The BCR opcodes are decoded from BCR bits 1−0, as shown in Table 3. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 3. Boundary-Control Register Opcodes BINARY CODE BIT 1 → BIT 0 MSB → LSB DESCRIPTION 00 Sample inputs/toggle outputs (TOPSIP) 01 Pseudo-random pattern generation/16-bit mode (PRPG) 10 Parallel-signature analysis/16-bit mode (PSA) 11 Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG) It should be noted, in general, that while the control input BSCs (bits 17−16) are not included in the sample, toggle, PSA, or PRPG algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive state (active or high impedance) of the device output terminals while the direction-control BSC (bit 17) controls which I/O ports, A or B, are considered input terminals and which are considered output terminals. sample inputs / toggle outputs (TOPSIP) Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK. pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK. This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Figure 5 illustrates the 16-bit linear-feedback shift-register algorithm through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns. I1 I2 I3 I4 I5 I6 I7 I8 O1 O2 O3 O4 O5 O6 O7 O8 = Figure 5. 16-Bit PRPG Configuration 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 parallel-signature analysis (PSA) Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs remains constant and is applied to the device outputs. Figure 6 illustrates the 16-bit linear-feedback shift-register algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation. I1 I2 I3 I4 I5 I6 I7 I8 O1 O2 O3 O4 O5 O6 O7 O8 = = Figure 6. 16-Bit PSA Configuration simultaneous PSA and PRPG (PSA / PRPG) Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 illustrates the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns. I1 I2 I3 I4 I5 I6 I7 I8 O1 O2 O3 O4 O5 O6 O7 O8 = = Figure 7. 8-Bit PSA / PRPG Configuration • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 13 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 timing description All test operations of the ’BCT8245A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK. A simple timing example is illustrated in Figure 8. In this example, the TAP controller begins in the Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 details the operation of the test circuitry during each TCK cycle. Table 4. Explanation of Timing Example TCK CYCLE(S) TAP STATE AFTER TCK DESCRIPTION 1 Test-Logic-Reset TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state. 2 Run-Test/Idle 3 Select-DR-Scan 4 Select-IR-Scan 5 Capture-IR The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state. 6 Shift-IR TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. 7−13 Shift-IR One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR. 14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 14 15 Update-IR 16 Select-DR-Scan 17 Capture-DR The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state. 18 Shift-DR TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. 19−20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO. 21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. In general, the selected data register is updated with the new data on the falling edge of TCK. Test operation completed • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Exit1-DR Capture-DR Exit1-IR Select-DR-Scan ÎÎ ÎÎ Update-IR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Shift-IR Capture-IR Select-IR-Scan TAP Controller State Select-DR-Scan TDO ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ Run-Test/Idle TDI Test-Logic-Reset TMS Shift-DR TCK 3-State (TDO) or Don’t Care (TDI) Figure 8. Timing Example absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI: I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V except I/O ports and TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range (TMS) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 12 V Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Input clamp current, IIK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA Current into any output in the low state: SN54BCT8245A (any A, TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SN54BCT8245A (any B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74BCT8245A (any A, TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74BCT8245A (any B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Maximum power dissipation at TA = 55° C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input voltage rating may be exceeded if the input clamp-current rating is observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 15 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 recommended operating conditions SN54BCT8245A SN74BCT8245A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIHH Double-high-level input voltage VIL Low-level input voltage 0.8 0.8 V IIK Input clamp current −18 −18 mA IOH High level output current High-level IOL Low level output current Low-level TA Operating free-air temperature 2 TMS 10 Any A, TDO 16 2 12 10 V 12 −3 −3 −12 −15 Any A, TDO 20 24 Any B 48 64 Any B −55 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 125 0 V 70 V mA mA °C SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54BCT8245A PARAMETER VIK Any A, TDO TEST CONDITIONS Any B TYP† SN74BCT8245A MAX II = −18 mA IOH = −1 mA 2.7 3.4 2.7 3.4 IOH = −1 mA 2.5 3.4 2.5 3.4 IOH = −3 mA 2.4 3.3 2.4 3.3 IOH = −3 mA 2.7 3.4 2.7 3.4 IOH = −3 mA 2.4 3.4 2.4 3.4 2 3.2 2 3.1 5V VCC = 4 4.5 VCC = 4.5 V VCC = 4 4.5 5V VOL Any B −1.2 IOH = −12 mA VCC = 4 4.5 5V IOL = 20 mA 0.3 0.5 0.38 0.55 0.35 IOL = 48 mA Any A or B IIH‡ IIHH TMS 5V VI = 5 5.5 VCC = 5.5 V, VI = 2.7 V VCC = 5.5 V, VI = 10 V 0.42 −1 −35 V V 0.5 0.55 0.1 0.1 0.25 0.25 −100 UNIT V IOL = 64 mA 5V VCC = 5 5.5 V, MAX −1.2 IOL = 24 mA Except A or B II TYP† VCC = 4.75 V, IOH = −15 mA Any A, A TDO MIN VCC = 4.5 V, VCC = 4.75 V, VOH MIN −1 −35 1 mA −100 μA 1 mA VCC = 5.5 V, VI = 0.5 V −30 −70 −200 −30 −70 −200 μA IOZH TDO VCC = 5.5 V, VO = 2.7 V −1 −35 −100 −1 −35 −100 μA IOZL TDO VCC = 5.5 V, VO = 0.5 V −30 −70 −200 −30 −70 −200 μA IOZPU VCC = 0 to 2 V, VO = 0.5 V or 2.7 V ±250 ±250 μA IOZPD VCC = 2 V to 0, VO = 0.5 V or 2.7 V ±250 ±250 μA Ioff VCC = 0, VI or VO ≤ 4.5 V ±250 ±250 μA VCC = 5.5 V, VO = 0 −225 mA IIL‡ IOS § −100 Outputs high ICC¶ VCC = 5 5.5 5V V, Outputs open −225 3.6 7.5 −100 3.6 7.5 Outputs low 35 52 35 52 Outputs disabled 1.5 3.5 1.5 3.5 mA Ci VCC = 5 V, VI = 2.5 V or 0.5 V 8 8 pF Cio VCC = 5 V, VO = 2.5 V or 0.5 V 14 14 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters I and I include the off-state output current. IH IL § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. ¶I CCH and ICCL are measured in the A-data to B-bus operational mode. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 17 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9) VCC = 5 V, TA = 25°C fclock Clock frequency tw Pulse duration tsu Setup time th Hold time td Delay time TCK SN54BCT8245A MIN MAX MIN MAX MIN MAX 0 20 0 20 0 20 TCK high or low 25 25 25 TMS double high 50* 50* 50 Any A or B before TCK↑ 6 6 6 DIR or OE before TCK↑ 6 6 6 TDI before TCK↑ 6 6 6 TMS before TCK↑ 12 12 12 Any A or B after TCK↑ 4.5 4.5 4.5 DIR or OE after TCK↑ 4.5 4.5 4.5 TDI after TCK↑ 4.5 4.5 4.5 TMS after TCK↑ Power up to TCK↑ 0 0 0 100* 100* 100 * On products compliant to MIL-PRF-38535, this parameter is not production tested. 18 SN74BCT8245A • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT MHz ns ns ns ns SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 9) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A or B B or A OE B or A OE B or A VCC = 5 V, TA = 25°C SN54BCT8245A SN74BCT8245A MIN TYP MAX MIN MAX MIN MAX 2 5.8 7.8 2 9.6 2 8.7 2 6.1 8.7 2 11 2 10 3 6.8 9.5 3 11.5 3 10.6 3 8.8 12.5 3 14.3 3 13.8 3 6.2 8.6 3 10.2 3 9.6 2.5 6 8 2.5 10.5 2.5 9.5 UNIT ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9) SN54BCT8245A PARAMETER FROM (INPUT) VCC = 5 V, TA = 25°C TO (OUTPUT) MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ MIN TYP MAX 6 13 15.5 6 21.5 6 12.5 15.5 6 21.5 3.5 7.6 10.5 3.5 14 3.5 8 10.5 3.5 13 7.5 16.5 20 7.5 28 7.5 17 21 7.5 29 6.5 14 17 6.5 24 7 15 20 7 26 3.5 7.6 10.5 3.5 11.5 4 8.5 12 4 17.5 8 18 22 8 30 8 19 25 8 32 6 14 18 6 24 6 14 18 6 23 3 8 11.5 3 13 3 7.5 10 3 13 8 18.5 22 8 31 8 18.5 22 8 31 TCK 20 TCK↓ B or A TCK↓ TDO TCK↑ B or A TCK↓ B or A TCK↓ TDO TCK↑ B or A TCK↓ B or A TCK↓ TDO TCK↑ B or A • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • MAX 20 UNIT MHz ns ns ns ns ns ns ns ns ns 19 SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9) SN74BCT8245A PARAMETER FROM (INPUT) VCC = 5 V, TA = 25°C TO (OUTPUT) MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ 20 TCK MIN TYP MAX 6 13 15.5 6 20 6 12.5 15.5 6 20 3.5 7.6 10.5 3.5 13 3.5 8 10.5 3.5 12 7.5 16.5 20 7.5 24 7.5 17 21 7.5 25 6.5 14 17 6.5 21 7 15 20 7 23 3.5 7.6 10.5 3.5 11 4 8.5 11 4 12.5 8 18 22 8 27 8 19 25 8 29 6 14 18 6 22 6 14 17 6 21 3 8 11.5 3 12.5 3 7.5 10 3 12 8 18.5 22 8 27 8 18.5 22 8 27 20 TCK↓ B or A TCK↓ TDO TCK↑ B or A TCK↓ B or A TCK↓ TDO TCK↑ B or A TCK↓ B or A TCK↓ TDO TCK↑ B or A • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • MAX 20 UNIT MHz ns ns ns ns ns ns ns ns ns SN54BCT8245A, SN74BCT8245A SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS043E − MAY 1990 − REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse 3V 1.5 V 1.5 V 0V 3V Timing Input 1.5 V tw 0V Data Input 3V th tsu Low-Level Pulse 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enable) 3V Input 1.5 V 1.5 V 0V VOH In-Phase Output 1.5 V Out-of-Phase Output 0V 3.5 V VOL tPLH tPHZ 0.3 V 1.5 V 0.3 V 0V tPZH VOH 1.5 V tPLZ 1.5 V Waveform 1 (see Notes B) 1.5 V VOL tPHL 1.5 V tPZL tPHL tPLH 1.5 V Waveform 2 (see Notes B) 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) VOH VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open. Figure 9. Load Circuits and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9172801Q3A ACTIVE LCCC FK 28 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629172801Q3A SNJ54BCT 8245AFK 5962-9172801QLA ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9172801QL A SNJ54BCT8245AJ T SN74BCT8245ADW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 BCT8245A Samples SN74BCT8245ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 BCT8245A Samples SNJ54BCT8245AFK ACTIVE LCCC FK 28 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629172801Q3A SNJ54BCT 8245AFK SNJ54BCT8245AJT ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9172801QL A SNJ54BCT8245AJ T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of