Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
SN74CB3T3125 Quadruple FET Bus Switch
2.5-V, 3.3-V Low-Voltage Bus Switch with 5-V-Tolerant Level Shifter
1 Features
3 Description
•
•
The SN74CB3T3125 is a high-speed TTL-compatible
FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. The device
fully supports mixed-mode signal operation on all
data I/O ports by providing voltage translation that
tracks VCC. The SN74CB3T3125 supports systems
using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS
switching standards, as well as user-defined
switching levels (see Typical DC Voltage-Translation
Characteristics).
1
•
•
•
•
•
•
•
•
•
•
•
•
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation On All
Data I/O Ports
– 5-V Input Down to 3.3-V Output-Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output-Level
Shift With 2.5-V VCC
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics
(ron = 5 Ω Typical)
Low Input/Output Capacitance Minimizes Loading
(Cio(OFF) = 4.5 pF Typical)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 20 μA Max)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels (0.8
V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or 5-V/3.3-V
CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
Supports Digital Applications: Level Translation,
USB Interface, Bus Isolation
Ideal for Low-Power Portable Equipment
The SN74CB3T3125 is organized as four 1-bit bus
switches with separate output-enable (1OE, 2OE,
3OE, 4OE) inputs. It can be used as four 1-bit bus
switches or as one 4-bit bus switch. When OE is low,
the associated 1-bit bus switch is ON, and the A port
is connected to the B port, allowing bidirectional data
flow between ports. When OE is high, the associated
1-bit bus switch is OFF, and the high-impedance
state exists between the A and B ports.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device
when it is powered down. The device has isolation
during power off.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
SN74CB3T3125
PACKAGE
BODY SIZE (NOM)
VQFN – RGY (14)
3.50 mm x 3.50 mm
TSSOP – PW (14)
5.00 mm x 4.40 mm
TVSOP – DGV (14)
3.60 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical DC Voltage-Translation Characteristics
VCC
5.5 V
VCC + 1 V
§9CC ± 1 V
0V
Input Voltages
IN
OUT
§9CC
CB3T
0V
Output Voltages
If the input high voltage (VIH) level is greater than or equal to VCC + 1 V, and less than or equal to 5.5 V, the output high voltage (VOH) level will
be equal to approximately the VCC voltage level.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2012) to Revision C
Page
•
Added Application list, Device Information table, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Changed ten VCC = 3.3 V MAX value From: 4.4 ns To: 8 ns in the Switching Characteristic ................................................. 5
Changes from Revision A (April 2009) to Revision B
•
2
Page
Updated Typical DC Voltage-Translation Characteristics ...................................................................................................... 1
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
DGV OR PW PACKAGE
(TOP VIEW)
1OE
1A
1B
2OE
2A
2B
GND
1
2
3
14
13
12
4
11
5
10
6
9
7
8
RGY PACKAGE
(TOP VIEW)
VCC
4OE
4A
4B
3OE
3A
3B
1A
1B
2OE
2A
2B
1OE
VCC
1
14
2
13
3
12
4
11
5
10
9
6
7
8
GND
3B
4OE
4A
4B
3OE
3A
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1OE
1
I
1A
2
I/O
Active-low enable for switch 1
Switch 1 A terminal
1B
3
I/O
Switch 1 B terminal
2OE
4
I
2A
5
I/O
Switch 2 A terminal
2B
6
I/O
Switch 2 B terminal
GND
7
-
3A
8
I/O
Switch 3 A terminal
3B
9
I/O
Switch 3 B terminal
3OE
10
I
4A
11
I/O
Switch 4 A terminal
4B
12
I/O
Switch 4 B terminal
4OE
13
I
Active-low enable for switch 4
VCC
14
-
Supply voltage pin
Active-low enable for switch 2
Ground
Active-low enable for switch 3
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
3
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range (2)
VCC
MIN
MAX
–0.5
7
UNIT
V
–0.5
7
V
–0.5
7
VIN
Control input voltage range
(2) (3)
VI/O
Switch I/O voltage range (2)
(3) (4)
IIK
Control input clamp current
VIN < 0
II/OK
I/O port clamp current
VI/O < 0
II/O
ON-state switch current (5)
Continuous current through VCC or GND
±100
mA
150
°C
Tstg
(1)
(2)
(3)
(4)
(5)
Storage temperature range
V
–50
mA
–50
mA
±128
mA
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCC
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
Supply voltage
UNIT
V
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74CB3T3125
THERMAL METRIC (1)
VQFN (RGY)
TSSOP (PW)
TVSOP (DGV)
UNIT
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
55.5
123.3
154.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.9
53.0
64.4
°C/W
RθJB
Junction-to-board thermal resistance
30.9
66.3
88.4
°C/W
ψJT
Junction-to-top characterization parameter
3.6
9.1
10.8
°C/W
ψJB
Junction-to-board characterization parameter
30.9
65.7
87.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
14.6
-
-
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
6.5 Electrical Characteristics (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VCC = 3 V, II = –18 mA
VOH
See Figure 3 through Figure 5
IIN
Control inputs
II
MIN TYP (2)
TEST CONDITIONS
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
VCC = 3.6 V, Switch ON, VIN = VCC or GND
(3)
VCC = 0, VO = 0 to 5.5 V, VI = 0
ICC
VCC = 3.6 V, II/O = 0, Switch ON or OFF,
VIN = VCC or GND
ΔICC
(4)
Cin
ron
VCC = 3 V, VI = 0
(1)
(2)
(3)
(4)
(5)
μA
10
μA
20
VI = 5.5 V
20
300
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND
(5)
μA
±10
VI = VCC or GND
VCC = 3.3 V, VIN = VCC or GND
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
μA
±5
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
VCC = 3.3 V, Switch ON, VIN = VCC or GND
±10
–40
Control inputs
Cio(ON)
V
VI = 0.7 V to VCC – 0.7 V
Control inputs
Cio(OFF)
–1.2
±20
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
Ioff
UNIT
VI = VCC – 0.7 V to 5.5 V
VI = 0 to 0.7 V
IOZ
MAX
VI/O = 5.5 V or 3.3 V
μA
μA
3
pF
4.5
pF
4
pF
VI/O = GND
10
IO = 24 mA
5
8
IO = 16 mA
5
8
IO = 64 mA
5
7
IO = 32 mA
5
7
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6)
PARAMETER
tpd
(1)
(1)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
0.15
UNIT
MAX
A or B
B or A
0.25
ns
ten
OE
A or B
1
8.5
1
8
ns
tdis
OE
A or B
1
9
1
9
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
5
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
4.0
4.0
3.0
3.0
V - Output Voltage - V
O
V - Output Voltage - V
O
6.7 Typical Characteristics
2.0
1.0
0.0
0.0
2.0
1.0
0.0
2.0
1.0
VCC = 2.3 V
4.0
3.0
6.0
5.0
VI - Input Voltage - V
IO = 1 µA
0.0
TA = 25°C
3.0
4.0
5.0
6.0
TA = 25°C
Figure 2. Data Output Voltage vs Data Input Voltage
4.0
VOH - Output Voltage High - V
4.0
VOH - Output Voltage High - V
2.0
VI - Input Voltage - V
IO = 1 µA
VCC = 3 V
Figure 1. Data Output Voltage vs Data Input Voltage
3.5
100 mA
3.0
8 mA
2.5
24 mA
16 mA
2.0
3.5
100 mA
3.0
8 mA
2.5
24 mA
2.3
2.5
2.7
2.9
3.1
3.3
3.5
VCC - Supply Voltage - V
= 2.3 V to 3.6 V
VI = 5.5 V
16 mA
2.0
1.5
VCC
1.0
1.5
2.3
3.7
TA = 85°C
VCC
Figure 3. Output Voltage High vs Supply Voltage
2.5
2.7
2.9
3.1
VCC - Supply Voltage - V
= 2.3 V to 3.6 V
VI = 5.5 V
3.3
3.5
3.7
TA = 25°C
Figure 4. Output Voltage High vs Supply Voltage
VOH - Output Voltage High - V
4.0
3.5
100 mA
3.0
8 mA
2.5
16 mA
24 mA
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
VCC - Supply Voltage - V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
3.5
3.7
TA = -40°C
Figure 5. Output Voltage High vs Supply Voltage
6
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
7 Parameter Measurement Information
VCC
Input Generator
VIN
50
50
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
GND
50
50
VG2
RL
CL
(see Note A)
VI
CL
500
500
3.6 V or GND
5.5 V or GND
30 pF
50 pF
2 × VCC
2 × VCC
500
500
GND
GND
30 pF
50 pF
0.15 V
0.3 V
Open
Open
500
500
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
TEST
VCC
S1
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
RL
Output
Control
(VIN)
V
VCC
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
VOH
VCC/2
VOH − VD
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as pd(s)
t
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 6. Test Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
7
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
8 Detailed Description
8.1 Overview
The SN74CB3T3215 device is organized as four 1-bit bus switches with separate ouput-enable (1OE, 2OE, 3OE,
and 4 OE) inputs. When OE is low, the associated 1-bit bus switch is ON, and the A port is connected to the B
port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF,
and a high-impedance state exists between the A and B ports. This device is fully specified for partial-powerdown applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device
when it is powered down. The SN74CB3T3125 device has isolation during power off. To ensure the highimpedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
1A
1OE
3A
3OE
2
SW
3
1B
1
2
2A
2OE
SW
8
3B
1
4A
4OE
5
6
SW
2B
4
12
11
SW
4B
13
Gate Voltage (VG) us approximately equal
To VCC + VT when the switch is ON and VI
>VCC + VT.
A
B
VGŸ
Control
Circuit
(1 Æ
Figure 7. Simplified Schematic, Each FET Switch (SW)
8
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
8.3 Feature Description
The SN74CB3T3125 is ideal for low-power portable equipment. Power consumption is low by design, ICC = 20
μA, On-state resistance is low (ron = 5 Ω) It has bidirectional data flow with near zero propagation delay. The
devices minimizes loading due to the low input/output capacitance Cio(OFF) = 4.5 pF Typical. Operating VCC
range from 2.3 V to 3.6 V. The output tracks VCC. Data and control inputs provide undershoot clamp diodes.
Control inputs can be driven by TTL or 5-V/3.3-V CMOS outputs. It supports mixed-mode signal operation on all
data I/O ports. Data I/Os support 0- to 5-V signaling levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V). The
device is protected from damaging current, Ioff supports partial shutdown which prevents the current from flowing
back through the device when it is powered down. In addition, it has 5-V tolerant I/Os with device powered up or
powered down. The device is latch-up resistant with 250 mA exceeding the JESD 17 standard, providing
protection from destruction due to latch-up. This device is protected against electrostatic discharge. It is tested
per JESD 22 using 2000-V Human-Body Model (A114-B, Class II), and 1000-V Charged-Device Model (C101).
8.4 Device Functional Modes
Table 1 lists the functional modes for the SN74CB3T3125.
Table 1. Function Table
(Each Bus Switch)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
1A
1OE
3A
3OE
2
SW
3
1B
1
2A
2OE
2
SW
1
8
3B
4A
4OE
5
SW
6
2B
4
12
SW
11
4B
13
Figure 8. Logic Diagram (Positive Logic)
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
9
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This application is specifically to connect a 5-V bus to a 3.3 V device. Ideally, set VCC to 3.3 V. It is assumed
that communication in this particular application is one-directional, going from the bus controller to the device.
9.2 Typical Application
1
Bus
Controller
2
3
5
6
7
4
8
0.1 µF
Figure 9. Application Circuit
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Because this design is for down-translating voltage, no
pull-up resistors are required.
9.2.2 Detailed Design Procedure
1. Recommended Input conditions – Specified high and low levels. See (VIH and VIL) in Recommended
Operating Conditions – Inputs are overvoltage tolerant allowing them to go as high as 7 V at any valid VCC.
2. Recommend output conditions – Load currents should not exceed 128 mA on each channel.
10
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
Typical Application (continued)
9.2.3 Application Curves
V - Output Voltage - V
O
4.0
3.0
2.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VI - Input Voltage - V
VCC = 3 V
IO = 1 µA
TA = 25°C
Figure 10. Data Output Voltage vs Data Input Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
11
SN74CB3T3125
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
www.ti.com
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 11 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 11. Example Layout
12
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
SN74CB3T3125
www.ti.com
SCDS120C – FEBRUARY 2003 – REVISED DECEMBER 2018
12 Device and Documentation Support
12.1 Device Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3125
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CB3T3125DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS125
Samples
SN74CB3T3125PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS125
Samples
SN74CB3T3125PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS125
Samples
SN74CB3T3125PWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS125
Samples
SN74CB3T3125RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
KS125
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
