SN74CB3T3384DW

     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 D Output Voltage Translation Tracks VCC D Supports Mixed-Mode Signal Operation On D D D D D D D VCC Operating Range From 2.3 V to 3.6 V D Data I/Os Support 0 to 5-V Signaling Levels All Data I/O Ports − 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC − 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered-Up or Powered-Down Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 40 µA Max) D D D D D D (For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V/2.5-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, Memory Interleaving, Bus Isolation Ideal for Low-Power Portable Equipment DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE description/ordering information ORDERING INFORMATION SOIC − DW −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SSOP (QSOP) − DBQ TSSOP − PW Tube SN74CB3T3384DW Tape and reel SN74CB3T3384DWR Tape and reel SN74CB3T3384DBQR Tube SN74CB3T3384PW Tape and reel SN74CB3T3384PWR TOP-SIDE MARKING CB3T3384 CB3T3384 KS384 TVSOP − DGV Tape and reel SN74CB3T3384DGVR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated    !"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+ $#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '0+ '+$%( #" +1&( !('$*%+!'( ('&!/&$/ 2&$$&!'3 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+ '+('!4 #" &.. ,&$&%+'+$( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 description/ordering information (continued) The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3384 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). VCC 5.5 V VCC IN ≈VCC − 1 V ≈VCC OUT ≈VCC − 1 V CB3T 0V 0V Input Voltages Output Voltages NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, the output high voltage (VOH) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC-Voltage-Translation Characteristics The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 5-bit bus switch) 2 INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 logic diagram (positive logic) 2 3 1A1 1B1 SW 10 11 1A5 1B5 SW 1 1OE 14 15 2A1 2B1 SW 22 23 2A5 SW 2B5 13 2OE simplified schematic, each FET switch (SW) † Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > VCC + VT. A B VG† Control Circuit EN‡ ‡ EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) VCC Supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI/O TA Data input/output voltage Operating free-air temperature MIN MAX 2.3 3.6 UNIT 1.7 5.5 2 5.5 0 0.7 0 0.8 0 5.5 V −40 85 °C V V V NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 3 V, II = −18 mA VOH See Figures 3 and 4 IIN Control inputs TYP† VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND MAX UNIT −1.2 V ±10 µA ±20 VI = VCC − 0.7 V to 5.5 V VI = 0.7 V to VCC − 0.7 V VCC = 3.6 V, Switch ON, VIN = GND II MIN −40 µA ±5 VI = 0 to 0.7 V IOZ‡ VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC ±10 µA Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA ICC ∆ICC§ Control inputs Cin Control inputs VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND VI = VCC or GND 40 VI = 5.5 V 40 A µA 300 µA VCC = 3.3 V, VIN = VCC or GND 3 pF Cio(OFF) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC 5 pF VCC = 3.3 V, Switch ON, VIN = GND VI/O = 5.5 V or 3.3 V Cio(ON) VI/O = GND 12 VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 IO = 24 mA 5 8 IO = 16 mA 5 8 VCC = 3 V, VI = 0 IO = 64 mA IO = 32 mA 5 7 5 7 ron¶ 4 pF Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER tpd† ten FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 1 10.5 1 UNIT MAX 0.25 ns 7.5 ns tdis OE A or B 1 6.5 1 8 ns † The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT Input Generator VI S1 RL VO 2 × VCC Open GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL V∆ tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V 5.5 V 30 pF 50 pF 0.15 V 0.3 V Output Control (VIN) VCC VCC/2 VCC/2 0V tPLZ tPZL Output Waveform 1 S1 at 2 × VCC (see Note B) VCC VCC/2 VOL tPHZ tPZH Output Waveform 2 S1 at Open (see Note B) VOL + V∆ VCC/2 VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 2. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs INPUT VOLTAGE 4.0 VCC = 2.3 V IO = 1 µA TA = 25°C 3.0 V − Output Voltage − V O V − Output Voltage − V O 4.0 2.0 1.0 0.0 VCC = 3 V IO = 1 µA TA = 25°C 3.0 2.0 1.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 VI − Input Voltage − V 2.0 Figure 3. Data Output Voltage vs Data Input Voltage 8 POST OFFICE BOX 655303 3.0 4.0 VI − Input Voltage − V • DALLAS, TEXAS 75265 5.0 6.0 
     

    

     
  SCDS159B − OCTOBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE V − Output Voltage High − V OH 3.5 4.0 VCC = 2.3 V ~ 3.6 V VI = 5.5 V TA = 85°C 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 VCC = 2.3 V ~ 3.6 V VI = 5.5 V TA = 25°C 3.5 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 VCC − Supply Voltage − V 3.5 3.7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4.0 V − Output Voltage High − V OH V − Output Voltage High − V OH 4.0 OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 3.5 VCC = 2.3 V to 3.6 V VI = 5.5 V TA = -40°C 100 µA 8 mA 16 mA 24 mA 3.0 2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC − Supply Voltage − V Figure 4. VOH Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74CB3T3384DBQR ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CB3T3384 Samples SN74CB3T3384DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T3384 Samples SN74CB3T3384DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB3T3384 Samples SN74CB3T3384PW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 Samples SN74CB3T3384PWG4 ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 Samples SN74CB3T3384PWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 Samples SN74CB3T3384PWRG4 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 KS384 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of