SN74CBT16209ADGVR

 
    


SCDS006O − NOVEMBER 1992 − REVISED NOVEMBER 2004 D Members of the Texas Instruments D D SN54CBT16209 . . . WD PACKAGE SN74CBT16209A . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels S0 1A1 1A2 GND 2A1 2A2 VCC 3A1 3A2 GND 4A1 4A2 5A1 5A2 GND 6A1 6A2 7A1 7A2 GND 8A1 8A2 9A1 9A2 description/ordering information The SN54CBT16209 and SN74CBT16209A devices provide 18 bits of high-speed TTL-compatible bus switching or exchanging. The low on-state resistance of the switches allows connections to be made with minimal propagation delay. The devices operate as an 18-bit bus switch or a 9-bit bus exchanger, which provides data exchanging between the four signal ports via the data-select (S0, S1, S2) terminals. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 S1 S2 1B1 1B2 2B1 2B2 GND 3B1 3B2 GND 4B1 4B2 5B1 5B2 GND 6B1 6B2 7B1 7B2 GND 8B1 8B2 9B1 9B2 ORDERING INFORMATION −55°C to 125°C TOP-SIDE MARKING Tube SN74CBT16209ADL Tape and reel SN74CBT16209ADLR TSSOP − DGG Tape and reel SN74CBT16209ADGGR CBT16209A TVSOP − DGV Tape and reel SN74CBT16209ADGVR CY209A CFP − WD Tube SNJ54CBT16209WD SSOP − DL −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA CBT16209A SNJ54CBT16209WD † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2004, Texas Instruments Incorporated   !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/  +#".)(&' ("$+-%& &" 5677 %-- +%#%$*&*#' %#* &*'&*. )-*'' "&0*#2'* "&*./  %-- "&0*# +#".)(&' +#".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
 
    


SCDS006O − NOVEMBER 1992 − REVISED NOVEMBER 2004 FUNCTION TABLE INPUTS 2 INPUTS/OUTPUTS S2 S1 S0 L L L L L H L FUNCTION A1 A2 L Z Z Disconnect H B1 Z A1 port = B1 port B2 Z A1 port = B2 port L H H Z B1 A2 port = B1 port H L L Z B2 A2 port = B2 port H L H Z Z Disconnect H H L B1 B2 A1 port = B1 port A2 port = B2 port H H H B2 B1 A1 port = B2 port A2 port = B1 port POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
    


SCDS006O − NOVEMBER 1992 − REVISED NOVEMBER 2004 logic diagram (positive logic) 1A1 1A2 9A1 2 46 3 45 1B1 1B2 23 26 24 25 9B1 9B2 9A2 1 S0 48 S1 47 S2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
 
    


SCDS006O − NOVEMBER 1992 − REVISED NOVEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54CBT16209 SN74CBT16209A MIN MAX MIN MAX 5.5 4 5.5 VCC VIH Supply voltage 4 High-level control input voltage 2 VIL TA Low-level control input voltage 2 −55 125 V V 0.8 Operating free-air temperature UNIT −40 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II ICC ∆ICC§ Control inputs Ci Control inputs Cio(OFF) TEST CONDITIONS MIN TYP‡ MAX UNIT −1.2 V VCC = 4.5 V, VCC = 0, II = −18 mA VI = 5.5 V VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V or GND IO = 0, VCC = 5.5 V, VI = 3 V or 0 One input at 3.4 V, 4 pF VO = 3 V or 0, VCC = 4 V TYP at VCC = 4 V S0, S1, and S2 = GND 7.5 pF VI = 2.4 V, II = 15 mA 14 20 II = 64 mA II = 30 mA 4 8 VI = 0 4 8 ron¶ VCC = 4.5 V 10 ±1 VI = VCC or GND Other inputs at VCC or GND µA A 3 µA 2.5 mA Ω VI = 2.4 V, II = 15 mA 6 15 ‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
 
    


SCDS006O − NOVEMBER 1992 − REVISED NOVEMBER 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54CBT16209 FROM (INPUT) PARAMETER TO (OUTPUT) tpd† A or B B or A tpd S A or B ten tdis S S SN74CBT16209A VCC = 4 V VCC = 5 V ± 0.5 V VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN MIN MIN MAX MAX MAX 0.8* 0.35 UNIT MAX 0.25 ns 14 2 13.1 9.9 1.5 9 ns A or B 16 1.7 15.3 10.3 1.5 9.8 ns A or B 14.5 1 13.2 9.3 1.5 8.8 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 500 Ω 3V Output Control LOAD CIRCUIT 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output Waveform 1 S1 at 7 V (see Note B) 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V 1.5 V VOH VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBT16209ADGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16209A SN74CBT16209ADGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY209A SN74CBT16209ADL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16209A SN74CBT16209ADLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16209A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of