SN74CBT16800CDGGR

     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 D Member of the Texas Instruments D D D D D D D D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family Undershoot Protection for Off-Isolation on A and B Ports Up To −2 V B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging Supports PCI Hot Plug Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating BIASV 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 description/ordering information The SN74CBT16800C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16800C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2003, Texas Instruments Incorporated   !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 description/ordering information (continued) The SN74CBT16800C is organized as two 10-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to BIASV through the equivalent of a 10-kΩ resistor when OE is high, or if the device is powered down (VCC = 0 V). During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION SSOP − DL −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − DGG Tube SN74CBT16800CDL Tape and reel SN74CBT16800CDLR Tube SN74CBT16800CDGG Tape and reel SN74CBT16800CDGGR TOP-SIDE MARKING CBT16800C CBT16800C TVSOP − DGV Tape and reel SN74CBT16800CDGVR CY800C † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 10-bit bus switch) 2 INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect B port = BIASV POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 logic diagram (positive logic) 1 1A1 1A10 46 2 SW 12 36 SW BIASV 1B1 1B10 48 1OE 35 13 SW 2A1 2A10 24 2B1 25 SW 2B10 47 2OE simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† † EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Bias supply voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX VCC BIASV Supply voltage 4 5.5 V Bias supply voltage 0 V VIH VIL High-level control input voltage 2 VCC 5.5 Low-level control input voltage 0 0.8 V VI/O TA Data input/output voltage 0 5.5 V −40 85 °C Operating free-air temperature UNIT V NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. BIASV is a supply voltage, not a control input. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Control inputs VCC = 4.5 V, VIKU Data inputs VCC = 5 V, VO(USP)‡ IIN = −18 mA 0 mA > II ≥ −50 mA, VIN = VCC or GND, MIN Switch OFF VCC = BIASV = 5 V, II = −10 mA, VIN = VCC or GND, Switch OFF B port VCC = 0 V, BIASV = Vx, IO = 0 IIN Control inputs VCC = 5.5 V, VIN = VCC or GND BIASV = 2.4 V, VO = 0, Switch OFF, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, VI = 0 Other inputs at VCC or GND B port VCC = 4.5 V, IOZ§ VCC = 5.5 V, Ioff VCC = 0, ICC VCC = 5.5 V, ∆ICC¶ Cin Control inputs VCC = 5.5 V, VIN = 3 V or 0 One input at 3.4 V, Control inputs Cio(OFF) A port VI/O = 3 V or 0, Switch OFF, VI/O = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V Cio(ON) ron# VCC = 4.5 V MAX UNIT −1.8 V −2 V 3 VO IO TYP† V Vx−0.1 Vx V ±1 µA 0.25 mA ±10 µA 10 µA 3 µA 2.5 mA Switch ON or OFF 4.5 pF VIN = VCC or GND 5.5 pF Switch ON, VIN = VCC or GND 15.5 pF VI = 2.4 V, IO = −15 mA 8 12 IO = 64 mA IO = 30 mA 3 6 VI = 0 3 6 Ω VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ VO(USP) = A-port undershoot static protection. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER TEST CONDITIONS tpd|| tPZH BIASV = GND tPZL BIASV = 3 V tPHZ BIASV = GND tPLZ BIASV = 3 V FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B OE A or B VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN MAX 0.24 UNIT MAX 0.15 6.5 1.5 6 6.5 1.5 6 6.5 1.5 6 6.5 1.5 6 ns ns ns || The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
     

   
  

    
  SCDS117C − JANUARY 2003 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 7V Input Generator VI S1 RL VO GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 50 pF 50 pF tPLZ/tPZL 5 V ± 0.5 V 4V 7V 7V 500 Ω 500 Ω GND GND 50 pF 50 pF 0.3 V 0.3 V tPHZ/tPZH 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC VCC 50 pF 50 pF 0.3 V 0.3 V Output Control (VIN) V∆ 3V 1.5 V 3V 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) 1.5 V 0V tPZL Output Control (VIN) Open VOL + V∆ VOL tPHZ 1.5 V VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 1. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBT16800CDGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16800C SN74CBT16800CDL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16800C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of