SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
D Standard ’126-Type Pinout (D, DB, DGV,
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4B
3OE
3A
3B
VCC
14
2
1
1A
1B
2OE
2A
2B
NC
1OE
1A
1B
2OE
2A
2B
GND
14
2
13 4OE
3
12 4A
4
11 4B
5
10 3OE
9 3A
6
7
8
3B
1
DBQ PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1OE
1OE
1A
1B
2OE
2A
2B
GND
JESD 17
GND
D
D TTL-Compatible Input Levels
D Latch-Up Performance Exceeds 250 mA Per
and PW Packages)
5-Ω Switch Connection Between Two Ports
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4OE
4A
4B
3OE
3A
3B
NC
NC − No internal connection
description/ordering information
The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
QFN − RGY
SN74CBT3126RGYR
Tube
SN74CBT3126D
Tape and reel
SN74CBT3126DR
SSOP − DB
Tape and reel
SN74CBT3126DBR
CU126
SSOP (QSOP) − DBQ
Tape and reel
SN74CBT3126DBQR
CU126
Tube
SN74CBT3126PW
Tape and reel
SN74CBT3126PWR
Tape and reel
SN74CBT3126DGVR
TSSOP − PW
TVSOP − DGV
†
TOP-SIDE
MARKING
Tape and reel
SOIC − D
−40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
CU126
CBT3126
CU126
CU126
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
Disconnect
H
A=B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
3
1B
1A
1
1OE
2A
2OE
5
6
4
9
8
3B
3A
3OE
10
12
11
4A
4OE
2B
4B
13
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN
MAX
5.5
VCC
Supply voltage
4
VIH
High-level control input voltage
2
VIL
Low-level control input voltage
TA
Operating free-air temperature
−40
UNIT
V
V
0.8
V
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VCC = 4.5 V,
II = −18 mA
II
VCC = 5.5 V,
VI = 5.5 V or GND
ICC
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
One input at 3.4 V,
Other inputs at VCC or GND
ΔICC‡
Control inputs
VCC = 5.5 V,
Ci
Control inputs
VI = 3 V or 0
Cio(OFF)
ron§
VO = 3 V or 0,
OE = GND
VCC = 4 V,
TYP at VCC = 4 V,
VCC = 4.5 V
VI = 0
VI = 2.4 V,
VI = 2.4 V,
II = 15 mA
TYP†
MAX
UNIT
−1.2
V
±1
μA
3
μA
2.5
mA
3
pF
4
pF
16
22
II = 64 mA
5
7
II = 30 mA
5
7
II = 15 mA
10
15
Ω
†
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC or GND.
§ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
VCC = 5 V
± 0.5 V
MIN
MIN
TO
(OUTPUT)
tpd¶
A or B
B or A
0.35
ten
OE
A or B
5.4
tdis
OE
A or B
5
PARAMETER
¶
VCC = 4 V
FROM
(INPUT)
MAX
UNIT
MAX
0.25
ns
1.6
5.1
ns
1
4.5
ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
tPHZ
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CBT3126D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBT3126
Samples
SN74CBT3126DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CU126
Samples
SN74CBT3126DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU126
Samples
SN74CBT3126DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBT3126
Samples
SN74CBT3126PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU126
Samples
SN74CBT3126PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU126
Samples
SN74CBT3126PWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU126
Samples
SN74CBT3126RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CU126
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of