SN74CBTH16211
24-BIT FET BUS SWITCH
WITH BUS HOLD
SCDS062C – JUNE 1998 – REVISED NOVEMBER 2001
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Bus Hold on Data Inputs/Outputs
Eliminates the Need for External
Pullup/Pulldown Resistors
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
VCC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
description
The SN74CBTH16211 provides 24 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as dual 12-bit bus
switches with separate output-enable (OE)
inputs. It can be used as two 12-bit bus switches
or one 24-bit bus switch. When OE is low, the
associated 12-bit bus switch is on, and the A port
is connected to the B port. When OE is high, the
switch is open, and a high-impedance state exists
between the two ports.
Active bus-hold circuitry is provided to hold
unused or floating A and B ports at a valid logic
level.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
NC – No internal connection
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74CBTH16211DL
Tape and reel
SN74CBTH16211DLR
TSSOP – DGG
Tape and reel
SN74CBTH16211DGGR
CBTH16211
TVSOP – DGV
Tape and reel
SN74CBTH16211DGVR
CYH211
SSOP – DL
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
CBTH16211
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBTH16211
24-BIT FET BUS SWITCH
WITH BUS HOLD
SCDS062C – JUNE 1998 – REVISED NOVEMBER 2001
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
2
54
1A1
1B1
14
42
1A12
1B12
56
1OE
15
41
2A1
2B1
28
29
2A12
2B12
55
2OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
VCC
VIH
Supply voltage
4
5.5
High-level control input voltage
2
VIL
TA
Low-level control input voltage
Operating free-air temperature
–40
UNIT
V
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTH16211
24-BIT FET BUS SWITCH
WITH BUS HOLD
SCDS062C – JUNE 1998 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Control inputs
II
All inputs
IBHL‡
IBHH§
IBHLO¶
IBHHO#
ICC
∆ICC||
Control inputs
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VCC = 4.5 V,
VCC = 0 V,
II = –18 mA
VI = 5.5 V
–1.2
V
VCC = 5.5 V,
VCC = 4.5 V,
VI = 5.5 V or GND
VI = 0.8 V
±10
VCC = 4.5 V,
VCC = 5.5 V,
±10
µA
100
µA
VI = 2 V
VI = 0 to 5.5 V
–100
µA
500
µA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0 to 5.5 V
IO = 0,
–500
µA
VCC = 5.5 V,
VCC = 4 V,
TYP at VCC = 4 V
One input at 3.4 V,
VI = VCC or GND
Other inputs at VCC or GND
VI = 2.4 V,
II = 15 mA
14
20
VI = 0
II = 64 mA
II = 30 mA
5
7
5
7
ronk
VCC = 4.5 V
3
µA
2.5
mA
Ω
VI = 2.4 V,
II = 15 mA
8
12
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
k Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
tpdh
ten
tdis
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
0.35
0.25
ns
OE
A or B
9.9
1
9.6
ns
OE
A or B
9.5
1
8.3
ns
MAX
UNIT
MAX
h The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBTH16211
24-BIT FET BUS SWITCH
WITH BUS HOLD
SCDS062C – JUNE 1998 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
500 Ω
3V
Output
Control
(low-level
enabling)
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
tPZH
tPHL
VOH
Output
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tr ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74CBTH16211DGGR
ACTIVE
TSSOP
DGG
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBTH16211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of