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SN74CBTLV3253PW

SN74CBTLV3253PW

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP16

  • 描述:

    IC MUX/DEMUX 2 X 4:1 16TSSOP

  • 数据手册
  • 价格&库存
SN74CBTLV3253PW 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 SN74CBTLV3253 Low-Voltage Dual 1-of-4 FET Multiplexer/Demultiplexer 1 Features 3 Description • • • • • The SN74CBTLV3253 device is a dual 1-of-4 highspeed FET multiplexer and demultiplexer. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. 1 Functionally Equivalent to QS3253 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II The select (S0, S1) inputs control the data flow. The FET multiplexers/demultiplexers are disabled when the associated output-enable (OE) input is high. The SN74CBTLV3253 device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. 2 Applications • • Video Broadcasting: IP-Based Multi-Format Transcoders Video Communications Systems Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74CBTLV3253D SOIC (16) 9.90 mm × 3.90 mm SN74CBTLV3253DBQ SSOP (16) 4.90 mm × 3.90 mm SN74CBTLV3253DGV TVSOP (16) 3.60 mm × 4.40 mm SN74CBTLV3253RGY VQFN (16) 4.00 mm × 3.50 mm SN74CBTLV3253PW TSSOP (16) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 7 1A 6 1B1 SW 5 SW 1B2 4 SW 1B3 3 1B4 SW 10 9 2A 2B1 SW 11 SW 2B2 12 2B3 SW 13 SW 2B4 14 S0 2 S1 1 1OE 15 2OE 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics .......................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes.......................................... 8 9 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application ................................................... 9 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 11 11.1 Layout Guidelines ................................................. 11 11.2 Layout Example .................................................... 11 12 Device and Documentation Support ................. 12 12.1 12.2 12.3 12.4 12.5 Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 12 12 12 12 12 13 Mechanical, Packaging, and Orderable Information ........................................................... 12 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (February 2014) to Revision J • Changed the Thermal Information table ................................................................................................................................. 4 Changes from Revision H (February 2014) to Revision I • 2 Page Updated data sheet – no specific changes ........................................................................................................................... 1 Changes from Revision F (July 2012) to Revision G • Page Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................................................................................................... 1 Changes from Revision G (February 2014) to Revision H • Page Page Deleted Ordering Information table. ....................................................................................................................................... 1 Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 SN74CBTLV3253 www.ti.com SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 5 Pin Configuration and Functions D, DBQ, DGV, or PW Package 16-Pin SOIC, SSOP, TVSOP, or TSSOP Top View 1OE S1 1B4 1B3 1B2 1B1 1A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE S0 2B4 2B3 2B2 2B1 2A VCC 1 16 15 2OE 14 S0 2 3 5 13 2B4 12 2B3 6 11 7 10 2B1 8 9 2A 4 GND S1 1B4 1B3 1B2 1B1 1A 1OE RGY Package 16-Pin VQFN Top View 2B2 Pin Functions PIN NAME NO. I/O DESCRIPTION 1OE 1 I Output Enable 1 Active-Low S1 2 I Select Pin 1 1B4 3 I/O Channel 1 I/O 4 1B3 4 I/O Channel 1 I/O 3 1B2 5 I/O Channel 1 I/O 2 1B1 6 I/O Channel 1 I/O 1 1A 7 I/O Channel 1 common GND 8 — Ground 2A 9 I/O Channel 2 common 2B1 10 I/O Channel 2 I/O 1 2B2 11 I/O Channel 2 I/O 2 2B3 12 I/O Channel 2 I/O 3 2B4 13 I/O Channel 2 I/O 4 S0 14 I Select Pin 0 2OE 15 I Output Enable 2 Active-Low VCC 16 — Power Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 3 SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage (2) VIN Control input voltage VI/O Switch I/O voltage (2) IIK Control input clamp current VIN < 0 II/OK I/O port clamp current VI/O < 0 MIN MAX UNIT –0.5 4.6 V –0.5 4.6 V –0.5 4.6 V –50 mA –50 mA Continuous current through VCC or GND ±128 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 6.2 ESD Ratings VESD (1) (2) Electrostatic discharge VALUE UNIT Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) +2000 V Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all pins (2) +1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage TA Operating free-air temperature (1) MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 –40 UNIT 85 V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information SN74CBTLV3253 THERMAL METRIC (1) D (SOIC) DBQ (SSOP) DGV (TVSOP) PW (TSSOP) RGY (VQFN) UNIT 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 86.7 112.4 123.1 110.9 47.1 °C/W RθJC(to Junction-to-case (top) thermal resistance 47.8 63.6 48.7 45.8 58.5 °C/W RθJB Junction-to-board thermal resistance 43.7 54.8 54.9 56.0 24.0 °C/W ψJT Junction-to-top characterization parameter 12.3 17.0 5.2 5.4 1.8 °C/W ψJB Junction-to-board characterization parameter 43.5 54.4 54.3 55.4 24.0 °C/W RθJC(b Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a 9.6 °C/W p) ot) (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 SN74CBTLV3253 www.ti.com SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK VCC = 3 V, II = –18 mA II VCC = 3.6 V, VI = VCC or GND Ioff VCC = 0, VI or VO = 0 to 3.6 V ICC VCC = 3.6 V, IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ∆ICC (2) Control inputs VCC = 3.6 V, Ci Control inputs VI = 3 V or 0 Cio(OFF) A port B port MAX UNIT –1.2 V ±1 µA 15 µA 10 µA 300 µA 3 VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0 pF 5.5 II = 64 mA VI = 0 VCC = 3 V pF 20.5 VI = 1.7 V, ron (3) VI = 2.4 V, (1) (2) (3) TYP (1) 5 8 II = 24 mA 5 8 II = 15 mA 27 40 II = 64 mA 5 7 II = 24 mA 5 7 II = 15 mA 10 15 Ω All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) A or B (1) B or A S A or B 1 6.8 1 ten S A or B 1 4.3 1 4 ns tdis S A or B 1 5.1 1 5.5 ns ten OE A or B 1 5 1 4.8 ns tdis OE A or B 1 5.5 1 5.4 ns PARAMETER tpd (1) MIN MAX MIN 0.15 UNIT MAX 0.25 5.5 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 5 SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com 6.7 Typical Characteristics 3 −40°C 25°C 85°C VO 2 1 0 0 1 2 3 VI Figure 1. VO vs VI, VCC = 2.5 V 6 Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 SN74CBTLV3253 www.ti.com SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 7 Parameter Measurement Information 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL CL 30 pF 50 pF VCC 2.5 V ±0.2 V 3.3 V ±0.3 V LOAD CIRCUIT V∆ 0.15 V 0.3 V RL 500 Ω 500 Ω VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL VOH Output VCC/2 VCC/2 VOL VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V tPLZ t Output PZL Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL VCC Output Control VCC/2 VCC VOL + V∆ VOL tPHZ tPZH VCC/2 VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Figure 2. Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 7 SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com 8 Detailed Description 8.1 Overview The SN74CBTLV3253 device is a dual 1-of-4 high-speed FET multiplexer/demultiplexer. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. The select (S0, S1) inputs control the data flow. The FET multiplexers and demultiplexers are disabled when the associated output-enable (OE) input is high. The SN74CBTLV3253 device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 7 6 1A SW 5 SW 1B1 1B2 4 SW 1B3 3 1B4 SW 10 9 2A 2B1 SW 11 SW 2B2 12 2B3 SW 13 2B4 SW 14 S0 2 S1 1 1OE 2OE 15 8.3 Feature Description The SN74CBTLV3253 device is functionally equivalent to the QS3253 and has a 5-Ω switch connection between two ports It also has rail-to-rail switching on data I/O ports as well as Ioff supporting partial-power-down mode operation 8.4 Device Functional Modes Table 1 lists the functional modes of the SN74CBTLV3253. Table 1. Function Table (Each Multiplexer/Demultiplexer) INPUTS 8 FUNCTION OE S1 S0 L L L A port = B1 port L L H A port = B2 port L H L A port = B3 port L H H A port = B4 port H X X Disconnect Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 SN74CBTLV3253 www.ti.com SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74CBTLV3253 can be used to multiplex and demultiplex up to 2 channels simultaneously in a 4:1 configuration. The application shown here is a 2-bit bus being multiplexed between two devices. the OE and S pins are used to control the chip from the bus controller. This is a very generic example, and could apply to many situations. 9.2 Typical Application µ 2 Figure 3. Typical Application of the SN74CBTLV3253 9.2.1 Design Requirements The 0.1µF capacitor should be placed as close as possible to the device. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – For specified high and low levels, see VIH and VIL in Recommended Operating Conditions . – Inputs and outputs are overvoltage tolerant slowing them to go as high as 4.6 V at any valid VCC. 2. Recommended Output Conditions: – Load currents should not exceed ±128 mA per channel. 3. Frequency Selection Criterion: – Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as directed in Layout. Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 9 SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com Typical Application (continued) 9.2.3 Application Curve 12 10 85°C 25°C ron 8 6 −40°C 4 2 0 0 0.5 1 1.5 2 2.5 3 VI Figure 4. ron vs VI, VCC = 2.5 V 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 10 Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 SN74CBTLV3253 www.ti.com SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 5 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. 11.2 Layout Example BETTER BEST 2W WORST 1W min. W Figure 5. Trace Example Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 11 SN74CBTLV3253 SCDS039J – DECEMBER 1997 – REVISED JANUARY 2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: Implications of Slow or Floating CMOS Inputs, SCBA004 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 12 Submit Documentation Feedback Copyright © 1997–2018, Texas Instruments Incorporated Product Folder Links: SN74CBTLV3253 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 74CBTLV3253PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL253 Samples SN74CBTLV3253D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3253 Samples SN74CBTLV3253DBQR ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL253 Samples SN74CBTLV3253DE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3253 Samples SN74CBTLV3253DGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL253 Samples SN74CBTLV3253DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3253 Samples SN74CBTLV3253PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL253 Samples SN74CBTLV3253PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CL253 Samples SN74CBTLV3253RGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CL253 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN74CBTLV3253PW 价格&库存

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