SN74GTL16612DL

SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com FEATURES • • • • • • • • • • Members of Texas Instruments Widebus™ Family UBT™ Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Identical to '16601 Function Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 500 mA Per JESD 17 SCBS480K – JUNE 1994 – REVISED JULY 2005 SN54GTL16612 . . . WD PACKAGE SN74GTL16612 . . . DGG OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND A18 OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA DESCRIPTION/ORDERING INFORMATION The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing ( VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) (2) (3) (4) SN54GTL16612 MIN NOM MAX MIN NOM MAX 3.3 V 3.15 3.3 3.45 3.15 3.3 3.45 5V 4.75 5 5.25 4.75 5 5.25 GTL 1.14 1.2 1.26 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 1.35 1.5 1.65 GTL 0.74 0.8 0.87 0.74 0.8 0.87 GTL+ 0.87 1 1.1 0.87 1 1.1 VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage B port VIL Low-level input voltage B port IIK Input clamp current IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) (2) (3) (4) 4 SN74GTL16612 B port VTT VTT Except B port 5.5 5.5 Except B port VREF + 50 mV VREF + 50 mV 2 2 UNIT V V V V V VREF – 50 mV VREF – 50 mV 0.8 0.8 –18 –18 mA A port –32 –32 mA A port 64 64 B port 40 40 Except B port –55 125 –40 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. V mA °C SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCBS480K – JUNE 1994 – REVISED JULY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V II = –18 mA VCC (3.3 V) = 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V IOH = –100 µA VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V A port VOL II VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V Cio (1) (2) (3) VCC (3.3 V) – 0.2 VCC (3.3 V) – 0.2 2.4 2.4 IOH = –32 mA 2 0.2 0.2 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 64 mA 0.6 0.55 Control inputs VCC (3.3 V) = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V VI = 5.5 V 10 10 1000 20 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VI = 5.5 V A port A port VI = VCC (3.3 V) VI = 0 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VI = VCC (3.3 V) VCC = 0, VI or VO = 0 to 4.5 V VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VI = 0 VI = 2 V 1 1 –30 –30 5 5 –5 –5 1000 100 75 75 –75 –75 VI = 0 to VCC (3.3 V) (2) VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 3 V 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V 10 10 A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V –1 –1 B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V –10 –10 Outputs high 1 1 Outputs low 5 5 Outputs disabled 1 1 Outputs high 120 120 Outputs low 120 120 Outputs disabled 120 120 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V Control inputs A port B port VI = 3.15 V or 0 VO = 3.15 V or 0 3.5 12 3.5 12 18 12 10 µA µA ±500 B port A or B port V µA ±500 A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND V 2 IOL = 100 µA 0.4 ∆ICC (3) Ci –1.2 0.5 ICC A or B (3.3 V) port ICC (5 V) –1.2 UNIT V IOH = –8 mA VI = 0.8 V IOZL MIN TYP (1) MAX VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 40 mA Ioff IOZH SN74GTL16612 MIN TYP (1) MAX B port B port II(hold) SN54GTL16612 µA µA mA mA mA pF 5 pF All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 5 SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCBS480K – JUNE 1994 – REVISED JULY 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) SN54GTL16612 MIN fclock tw tsu th SN74GTL16612 MAX Clock frequency MIN MAX 95 Pulse duration Setup time Hold time 95 LEAB or LEBA high 3.3 3.3 CLKAB or CLKBA high or low 5.6 5.6 A before CLKAB↑ 1.3 1.3 B before CLKBA↑ 3.4 2.5 A before LEAB↓ 1.2 0 B before LEBA↓ 1 1 CEAB before CLKAB↑ 2.1 2 CEBA before CLKBA↑ 2.6 2.2 A after CLKAB↑ 2.9 1.6 B after CLKBA↑ 4.1 0.3 A after LEAB↓ 4.5 4 B after LEBA↓ 4.3 3.6 CEAB after CLKAB↑ 2 0.8 CEBA after CLKBA↑ 1.1 1.1 UNIT MHz ns ns ns Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER SN54GTL16612 MIN TYP (1) SN74GTL16612 MAX MIN TYP (1) MAX fmax 95 1 2.8 4.5 1.5 2.8 4.1 1 2.5 4.5 1.3 2.5 4 1 3.6 5.5 2 3.6 5.3 1 3.5 6 1.9 3.5 5.4 1 3.7 5.5 2.3 3.7 5.3 1 3.4 5.5 1.9 3.4 5.4 1 3.3 5.5 2 3.3 5.5 1 3.4 5.5 2 3.4 5.1 tPLH tPHL tPLH tPHL ten tdis A B LEAB B CLKAB B OEAB B tr Transition time, B outputs (0.5 V to 1 V) tf Transition time, B outputs (1 V to 0.5 V) tPLH tPHL tPLH tPHL tPLH tPHL ten tdis 6 TO (OUTPUT) tPLH tPHL (1) FROM (INPUT) B A LEBA A CLKBA A OEBA A All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. 95 1.3 MHz 1.3 0.5 UNIT ns ns ns ns ns 0.5 ns 2 4.1 6.9 2.1 4.1 6.3 1 2.9 5.1 1.2 2.9 4.6 2 3.7 6.1 2.3 3.7 5.7 1 3 5.1 1.8 3 4.8 2 3.8 6.4 2.5 3.8 6.1 2 3.3 5.6 2.3 3.3 5.2 1 5 7.5 2.3 5 7.4 2 4.3 6.9 2.5 4.3 6.4 ns ns ns ns SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCBS480K – JUNE 1994 – REVISED JULY 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) SN54GTL16612 MIN fclock tw tsu th SN74GTL16612 MAX Clock frequency MIN MAX 95 Pulse duration Setup time Hold time 95 LEAB or LEBA high 3.3 3.3 CLKAB or CLKBA high or low 5.6 5.6 A before CLKAB↑ 1.3 1.3 B before CLKBA↑ 3.2 2.3 A before LEAB↓ 1.2 0 B before LEBA↓ 1.3 1.3 CEAB before CLKAB↑ 2.1 2 CEBA before CLKBA↑ 2.6 2.2 A after CLKAB↑ 2.9 1.6 B after CLKBA↑ 4.4 0.3 A after LEAB↓ 4.5 4 B after LEBA↓ 4.3 3.6 CEAB after CLKAB↑ 2 0.8 CEBA after CLKBA↑ 1.1 1.1 UNIT MHz ns ns ns Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER TO (OUTPUT) SN54GTL16612 MIN TYP (1) SN74GTL16612 MAX MIN TYP (1) MAX fmax 95 tPLH 1 2.8 4.5 1.5 2.8 4.1 1 2.5 4.6 1.3 2.5 4.1 1 3.6 5.5 2 3.6 5.3 1 3.5 6.1 1.9 3.5 5.5 1 3.7 5.5 2.3 3.7 5.3 1 3.4 5.6 1.9 3.4 5.5 1 3.4 5.5 2 3.4 5.1 1 3.3 5.6 2 3.3 5.6 tPHL tPLH tPHL tPLH tPHL tPLH tPHL A B LEAB B CLKAB B OEAB B tr Transition time, B outputs (0.5 V to 1 V) tf Transition time, B outputs (1 V to 0.5 V) tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) FROM (INPUT) B A LEBA A CLKBA A OEBA A 95 1.5 MHz 1.5 0.8 UNIT ns ns ns ns ns 0.8 ns 1.9 4 6.9 2 4 6.3 0.9 2.8 4.9 1.1 2.8 4.4 2 3.7 6.1 2.3 3.7 5.7 1 3 5.1 1.8 3 4.8 2 3.8 6.4 2.5 3.8 6.1 2 3.3 5.6 2.3 3.3 5.2 1 5 7.5 2.3 5 7.4 2 4.3 6.9 2.5 4.3 6.4 ns ns ns ns All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. 7 SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS www.ti.com SCBS480K – JUNE 1994 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V for GTL+ VTT 6V From Output Under Test CL = 50 pF (see Note A) S1 500 Ω Open 25 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND 500 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS LOAD CIRCUIT FOR B OUTPUTS tw 3V VM V Input 3V Timing Input 1.5 V 0V VM V tsu 0V VOLTAGE WAVEFORMS PULSE DURATION (VM = 1.5 V for A port and VREF for B port)(1) 3V Input (see Note B) 1.5 V Test Point th 3V Data Input A Port 1.5 V Data Input B Port VREF 0V VTT VREF 0V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL tPLH VTT Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port)(1) VREF VREF 0V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port)(1) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note C) tPHL tPLH 1.5 V tPZL VTT Input (see Note B) 3V Output Control (see Note B) Output Waveform 2 S1 at GND (see Note C) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) (1) All control inputs are TTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74GTL16612DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GTL16612 SN74GTL16612DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GTL16612 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of