SN74GTL2003
SCDS305D – FEBRUARY 2011 – REVISED SEPTEMBER 2022
SN74GTL2003 8-Bit Bidirectional Low-Voltage Translator
1 Features
3 Description
•
The SN74GTL2003 device provides eight NMOS pass
transistors (Sn and Dn) with a common gate (GREF)
and a reference transistor (SREF and DREF). The low
ON-state resistance of the switch allows connections
to be made with minimal propagation delay. With
no direction control pin required, the device allows
bidirectional voltage translations any voltage (0.95 V
to 5 V) to any voltage (0.95 V to 5 V).
•
•
•
•
•
•
•
•
•
Provides bidirectional voltage translation with no
direction control required
Allows voltage level translation
from 0.95 V up to 5 V
Provides direct interface with GTL, GTL+, LVTTL/
TTL, and 5-V CMOS levels
Supports 50 MHz up or down translation at ≦20 pF
capacitive load
Low ON-state resistance between input and output
pins (Sn/Dn)
Supports hot insertion
No power supply required – will not latch up
5-V-tolerant inputs
Low standby current
Flow-through pinout for ease of printed circuit
board trace routing
All transistors in the SN74GTL2003 have the
same electrical characteristics, and there is minimal
deviation from one output to another in voltage or
propagation delay. This offers superior matching over
discrete transistor voltage-translation solutions where
the fabrication of the transistors is not symmetrical.
With all transistors being identical, the reference
transistor (SREF/DREF) can be located on any of
the other eight matched Sn/Dn transistors, allowing
for easier board layout. The translator transistors
with integrated ESD circuitry provides excellent ESD
protection.
2 Applications
•
•
•
•
•
•
•
Bidirectional or unidirectional applications requiring
voltage-level translation from any voltage
(0.95 V to 5 V) to any voltage (0.95 V to 5 V)
Low voltage processor I2C port translation to 3.3-V
or 5-V I2C bus signal levels
GTL/GTL+ translation to LVTTL/TTL signal levels
HPC server
Dialysis machines
Service router
Servers
DREF
SREF
GREF
Package Information(1)
PART NUMBER
SN74GTL2003
(1)
PACKAGE
BODY SIZE (NOM)
PW (TSSOP, 20)
6.50 mm × 4.40 mm
RKS (VQFN, 20)
4.50 mm × 2.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
D1
D8
S1
S8
SA00647
Simplified Clamp Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74GTL2003
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SCDS305D – FEBRUARY 2011 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Switching Characteristics ...........................................5
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Applications.................................................. 10
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Receiving Notification of Documentation Updates..17
12.2 Receiving Notification of Documentation Updates..17
12.3 Support Resources................................................. 17
12.4 Trademarks............................................................. 17
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2016) to Revision D (September 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated definition of the switching characteristics table.................................................................................... 5
Changes from Revision B (June 2015) to Revision C (September 2016)
Page
• Updated Features .............................................................................................................................................. 1
• Updated pinout images to new format................................................................................................................ 3
• Added Receiving Notification of Documentation Updates section....................................................................17
Changes from Revision A (March 2013) to Revision B (June 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
2
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20
1
GND
GREF
5 Pin Configuration and Functions
SREF
2
19
DREF
S1
3
18
D1
S2
4
17
D2
S3
5
16
D3
Thermal
GND
1
20
GREF
SREF
2
19
DREF
S1
3
18
D1
S2
4
17
D2
S3
5
16
D3
Pad
6
15
D4
S4
6
15
D4
S5
7
14
D5
S5
7
14
D5
S6
8
13
D6
S6
8
13
D6
S7
9
12
D7
S7
9
12
D7
S8
10
11
D8
Not to scale
D8
S8
10
11
S4
Not to scale
Figure 5-1. RKS Package, 20-Pin VQFN (Top View)
Figure 5-2. PW Package, 20-Pin TSSOP (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
D1
18
I/O
GTL drain port
D2
17
I/O
GTL drain port
D3
16
I/O
GTL drain port
D4
15
I/O
GTL drain port
D5
14
I/O
GTL drain port
D6
13
I/O
GTL drain port
D7
12
I/O
GTL drain port
D8
11
I/O
GTL drain port
DREF
19
—
Drain of reference transistor, tie directly to GREF and pull up to reference voltage through a
200-kΩ resistor
GND
1
—
Ground
GREF
20
—
Gate of reference transistor, tie directly to DREF and pull up to reference voltage through a 200-kΩ
resistor
S1
3
I/O
LVTTL/TTL source port
S2
4
I/O
LVTTL/TTL source port
S3
5
I/O
LVTTL/TTL source port
S4
6
I/O
LVTTL/TTL source port
S5
7
I/O
LVTTL/TTL source port
S6
8
I/O
LVTTL/TTL source port
S7
9
I/O
LVTTL/TTL source port
S8
10
I/O
LVTTL/TTL source port
SREF
2
—
Source of reference transistor
(1)
I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VSREF
DC source reference voltage
–0.5
7
V
VDREF
DC drain reference voltage
–0.5
7
V
VGREF
DC gate reference voltage
–0.5
7
V
VSn
DC voltage port Sn
–0.5
7
V
VDn
DC voltage port Dn
–0.5
7
V
IREFK
DC diode current on reference pins
VI < 0 V
–50
mA
ISK
DC diode current port Sn
VI < 0V
–50
mA
IDK
DC diode current port Dn
VI < 0 V
–50
mA
IMAX
DC clamp current per channel
Channel is ON state
±128
mA
Tstg
Storage temperature
150
°C
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VI/O
MIN
MAX
0
5.5
V
Input/output voltage (Sn, Dn)
voltage(1)
UNIT
VSREF
DC source reference
0
5.5
V
VDREF
DC drain reference voltage
0
5.5
V
VGREF
DC gate reference voltage
0
5.5
V
IPASS
Pass transistor current
64
mA
TA
Operating ambient temperature (in free air)
85
°C
(1)
–40
VSREF = VDREF – 1.5 V for best results in level-shifting applications.
6.4 Thermal Information
SN74GTL2003
THERMAL
PW (TSSOP)
RKS (VQFN)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
83
81
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32
36
°C/W
(1)
4
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
VOL
Low-level output voltage
VDD = 3 V, VSREF = 1.365 V, VSn or VDn = 0.175 V,
Iclamp = 15.2 mA
VIK
Input clamp voltage
II = –18 mA
VGREF = 0 V
IIH
Gate input leakage
VI = 5 V
VGREF = 0 V
CI(GREF)
Gate capacitance
VI = 3 V or 0 V
CIO(OFF)
OFF capacitance
VO = 3 V or 0 V
CIO(ON)
ON capacitance
VO = 3 V or 0 V
VI = 0 V
ron (2)
TYP(1)
MAX
UNIT
260
350
mV
–1.2
V
5
µA
56
pF
VGREF = 0 V
7.4
pF
VGREF = 3 V
18.6
pF
VGREF = 4.5 V
3.5
5
VGREF = 3 V
4.4
7
VGREF = 2.3 V
IO = 64 mA
VGREF = 1.5 V
ON-state resistance
VGREF = 1.5 V,
VI = 2.4 V
VI = 1.7 V
(1)
(2)
MIN
IO = 30 mA
VGREF = 4.5 V
VGREF = 3 V
IO = 15 mA
VGREF = 2.3 V
5.5
9
67
105
9
15
7
10
58
80
50
70
Ω
All typical values are measured at TA = 25°C.
Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals.
6.6 Switching Characteristics
VREF = 1.365 V to 1.635 V, VDD1 = 3 V to 3.6 V, VDD2 = 2.36 V to 2.64 V, GND = 0 V, tr = tf ≤ 3 ns, TA = –40°C to +85°C
(see Figure 9-1)(1)
PARAMETER
tPLH
(1)
(2)
(3)
(3)
Propagation delay (Sn to Dn, Dn to Sn)
MIN
TYP(2)
MAX
0.5
1.5
5.5
MIN
TYP
MAX
UNIT
ns
CON(max) of 30 pF and a COFF(max) of 15 pF is specified by design.
All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and TA = 25°C.
Propagation delay specified by characterization.
6.7 Switching Characteristics
VGREF = 5 V ± 0.5 V, GND = 0 V, TA = –40°C to +85°C
(see Figure 9-1)
PARAMETER
tPD
(1)
Propagation
delay(1)
250
UNIT
ps
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON-state
resistance of the switch and a load capacitance of 50 pF, when driven by a voltage source with zero output impedance.
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6.8 Typical Characteristics
70
On-State Resistance ( )
60
50
40
30
20
Vi = 0V
Vi = 2.4V
Vi = 1.7V
10
0
0
1
2
3
4
5
6
7
GREF (V)
8
9
10
C001
Figure 6-1. ON-Resistance vs GREF Typical Curves
6
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7 Parameter Measurement Information
CL = Load Capacitance, includes jig and probe capacitance (see Section 6.5 for value)
VDD2
AC Waveforms
Vm = 1.5 V, VIN = GND to 3 V
200
VI
Input
VDD2
VM
VM
tPHL0
tPLH0
150
VDD2
150
150
DUT
GND
VDD2
VDD2
VM
Low-to-High
VOL
tPHL
SREF
S1 . . . S8
tPLH
tPLH1
VM
Low-to-High
VOL
D1 . . . D8
VM
tPHL1
VDD2
DREF GREF
VM
Figure 7-1. Input (Sn) to Output (Dn) Propagation
Delays
Test
Jig
VREF
Pulse
Generator
Figure 7-2. Load Circuit
AC Waveforms
From Ouput
Under Test
3V
Input
1.5 V
1.5 V
tPLH
tPHL
CL = 50 pF
0V
500
S1
7V
500
Figure 7-4. Load Circuit
VOH
Output
1.5 V
1.5 V
VOL
Figure 7-3. Input (Sn) to Output (Dn) Propagation
Delays
Table 7-1. Test Conditions
TEST
S1
tpd
Open
tPLZ/tPZL
7V
TPHZ/TPZH
Open
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8 Detailed Description
8.1 Overview
The SN74GTL2003 device provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a
reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage
translations from any voltage (0.95 V to 5 V) to any voltage (0.95 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port
is pulled to VCC by the pullup resistors.
8.2 Functional Block Diagram
20
GREF
SREF
2
19 D
REF
S1
3
18 D
1
4
17
5
16
S2
S3
D2
D3
8.3 Feature Description
8.3.1 Provides Bidirectional Voltage Translation With No Direction Control Required
Because the circuit acts essentially as a pass transistor, no direction pin is needed, as data is allowed to flow
both ways.
8.3.2 Flow Through Pinout
Allocated pins for input and output A on right side and input and output B on left side. Reduces the need for
multi-layer board layout or long traces through the system.
8
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8.4 Device Functional Modes
Table 8-1. High to Low Translation
(Assuming Dn is at the Higher Voltage Level)
(1)
(2)
(3)
(4)
GREF (1)
DREF
SREF
INPUTS
D8–D1
OUTPUT S8–
S1
TRANSISTOR
H
H
0V
X
X
Off
VTT
(2)
H
VTT
(3)
H
H
H
H
VTT
L
L(4)
On
On
L
L
0 – VTT
X
X
Off
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
Table 8-2. Low to High Translation
(Assuming Dn is at the Higher Voltage Level)
(1)
(2)
(3)
(4)
INPUTS
D8–D1
OUTPUT S8–
S1
GREF(1)
DREF
H
H
0V
X
X
Off
H
H
VTT (2)
VTT
H(3)
Nearly Off
H
H
VTT
L
L(4)
On
L
L
0 – VTT
X
X
Off
SREF
TRANSISTOR
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Dn is pulled up to VCC through an external resistor.
Dn follows the Sn input LOW.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
SN74GTL2003 is a GTL/GTL+ to LVTTL/TTL bidirectional voltage level translator. This device can be used
in both unidirectional applications and bidirectional. Please find the reference schematics and recommended
values for passive components in Section 9.2.
9.2 Typical Applications
9.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor
(typically 200 kΩ). TI recommends a filter capacitor on DREF. The processor output can be totem pole or open
drain (pullup resistors) and the chipset output can be totem pole or open drain (pullup resistors are required
to pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the
outputs must be 3-statable, and the outputs must be controlled by some direction-control mechanism to prevent
HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The
opposite side of the reference transistor (SREF) is connected to the processor core power-supply voltage. When
DREF is connected through a 200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set from 1 V to VCC
1.5 V, the output of each Sn has a maximum output voltage equal to SREF, and the output of each Dn has a
maximum output voltage equal to VCC.
VDPU = 5 V
200K Ω
VREF = 1.8V
GTL2003
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
D1
SW
CPU I/O
Chipset
I/O
S2
D2
SW
VDPU = 3.3V
RPU
S7
D7
S8
D8
RPU
Chipset
I/O
GND
Figure 9-1. Bidirectional Translation to Multiple Higher Voltage Levels
(Such as an I2C or SMBus Applications)
10
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9.2.1.1 Design Requirements
•
•
•
•
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of ≅200 kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in Section 6.3.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Resistor value (W ) =
Pullup voltage (V ) - 0.35 V
0.015 A
(1)
Table 9-1 provides resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage
of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 9-1. Pullup Resistor Values(1) (2) (3) (4)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
(4)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
H = HIGH voltage level, L = LOW voltage level, X = do not care.
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
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9.2.1.3 Application Curve
6
Voltage (V)
5
4
3
2
1
CPU I/O
Chipset I/O
0
0
100 200 300 400 500 600 700 800 900 1000
Time (ps)
C001
Figure 9-2. Signal Voltage vs Time (ps) (Simulated Design Results)
9.2.2 Unidirectional Down Translation
For unidirectional clamping (higher voltage to lower voltage), the GREF input must be connected to DREF and
both pins pulled to the higher-side VCC through a pullup resistor (typically 200 kΩ). TI recommends a filter
capacitor on DREF. Pullup resistors are required if the chipset I/Os are open drain. The opposite side of the
reference transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected
through a 200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set from 1 V to VCC – 1.5 V, the output of
each Sn has a maximum output voltage equal to SREF.
VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
DREF
SREF
S1
GREF
SW
D1
CPU I/O
S2
D2
Chipset
I/O
SW
Sn
Dn
GND
Figure 9-3. Unidirectional Down Translation to Protect Low-Voltage Processor Pins
9.2.2.1 Design Requirements
•
•
•
•
12
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of ≅200 kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in Section 6.3.
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9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Resistor value (W ) =
Pullup voltage (V ) - 0.35 V
0.015 A
(2)
Table 9-2 provides resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage
of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 9-2. Pullup Resistor Values(1) (2) (3) (4)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
(4)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
H = HIGH voltage level, L = LOW voltage level, X = do not care.
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
9.2.3 Unidirectional Up Translation
For unidirectional up translation (lower voltage to higher voltage), the reference transistor is connected the same
as for a down translation. A pullup resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH
level, because the GTL device only passes the reference source (SREF) voltage as a HIGH when doing an up
translation. The driver on the lower voltage side only needs pullup resistors if it is open drain.
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VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
SW
D1
CPU I/O
Chipset
I/O
S2
SW
Sn
D2
Dn
GND
Figure 9-4. Unidirectional Up Translation to Higher-Voltage Chipsets
9.2.3.1 Design Requirements
•
•
•
•
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of ≅200 kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in Section 6.3
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Resistor value (W ) =
Pullup voltage (V ) - 0.35 V
0.015 A
(3)
Table 9-3 provides resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage
of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 9-3. Pullup Resistor Value(1) (2) (3) (4)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
14
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
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Table 9-3. Pullup Resistor Value(1) (2) (3) (4) (continued)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
(4)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
H = HIGH voltage level, L = LOW voltage level, X = do not care.
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
10 Power Supply Recommendations
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Minimize trace
as possible
GND 1
20 GREF
SREF 2
19 DREF
S1
3
18 D1
S2
4
17 D2
S3
5
VDD
Minimize stub
as possible
16 D3
SN74GTL2003
S4
6
15 D4
S5
7
14 D5
S6
8
13 D6
S7
9
12 D7
S8
10
11 D8
Figure 11-1. Layout Example for GTL Trace
16
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74GTL2003PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
GK2003
Samples
SN74GTL2003PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
GK2003
Samples
SN74GTL2003RKSR
ACTIVE
VQFN
RKS
20
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
GK2003
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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