SN54HC112, SN74HC112
SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
1 Features
2 Description
•
•
•
•
•
•
The ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets the
outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J
and K inputs meeting the setup time requirements are
transferred to the outputs on the negative-going edge
of the clock (CLK) pulse. Clock triggering occurs at a
voltage level and is not directly related to the fall time
of the CLK pulse. Following the hold-time interval,
data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flipflops perform as toggle flip-flops by tying J and K high.
Wide operating voltage range of 2 V to 6 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 40-μA max ICC
Typical tpd = 13 ns
±4-mA output drive at 5 V
Low input current of 1 μA max
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN54HC112J
CDIP (16)
24.38 mm × 6.92 mm
SN74HC112D
SOIC (16)
9.90 mm × 3.90 mm
SN74HC112N
PDIP (16)
19.31 mm × 6.35 mm
SN54HC112FK
LCCC (20)
8.89 mm × 8.45 mm
SN54HC112W
CFP (16)
10.16 mm × 6.73 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC112, SN74HC112
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(2) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................6
5.5 Timing Requirements.................................................. 6
5.6 Switching Characteristics ...........................................7
5.7 Operating Characteristics........................................... 7
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2022) to Revision H (June 2022)
Page
• Junction-to-ambient thermal resistance values increased. D was 73 is now 117.2, N was 67 is now 89.1........4
Changes from Revision F (September 2003) to Revision G (February 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
4 Pin Configuration and Functions
J, D, N, W package
16-Pin CDIP, SOIC, PDIP, CFP
Top View
FK Package
20-Pin LCCC
Top View
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
mA
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
℃
150
℃
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(2)
SN54HC112
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
NOM
MAX
2
5
6
Low-level input voltage
VI
Input voltage
VO
Output voltage
TA
(1)
(2)
MAX
2
5
6
3.15
3.15
4.2
4.2
VCC = 4.5 V
0
0.5
0.5
1.35
0
VCC
0
V
VCC
V
VCC = 4.5 V
500
500
VCC = 6 V
400
400
125
V
VCC
1000
−55
V
1.8
VCC
1000
Operating free-air temperature
UNIT
V
1.35
1.8
0
VCC = 2 V
Input transition (rise and fall) time
NOM
1.5
VCC = 6 V
tt (1)
MIN
1.5
VCC = 2 V
VIL
SN74HC112
MIN
−40
85
ns
°C
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state
from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
4
(1)
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
117.2
89.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
77.2
46.9
°C/W
RθJB
Junction-to-board thermal resistance
75.6
47.4
°C/W
ψJT
Junction-to-top characterization parameter
38.1
11.8
°C/W
ψJB
Junction-to-board characterization parameter
75.3
47
°C/W
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
5.3 Thermal Information (continued)
THERMAL METRIC
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
D (SOIC)
N (PDIP)
16 PINS
16 PINS
UNIT
N/A
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = −20 μA
VOH
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
VI = VCC or 0
VI = VCC or 0,
MAX
MIN
MAX
UNIT
V
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
4
80
40
μA
10
10
10
pF
IOL = 5.2 mA
II
MIN
IOL = 20 μA
VI = VIH or VIL
ICC
MAX
SN74HC112
TYP
IOH = −5.2 mA
VOL
SN54HC112
MIN
VI = VIH or VIL
IOH = −4 mA
TA = 25°C
IO = 0
6V
Ci
2 V to 6 V
3
V
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
TA = 25°C
MIN
tw
Pulse duration
CLK high or low
Data (J, K)
tsu
Setup time before CLK↓
PRE or CLR inactive
th
6
Hold time, data after CLK↓
MIN
SN74HC112
MAX
MIN
MAX
2V
5
3.4
4
4.5 V
25
17
20
6V
PRE or CLR low
SN54HC112
MAX
29
20
MHz
24
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
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UNIT
ns
ns
ns
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
PRE or CLR
Q or Q
tpd
CLK
tt
Q or Q
Q or Q
VCC
TA = 25°C
MIN
TYP
SN54HC112
MAX
MIN
SN74HC112
MAX
MIN
2V
5
10
3.4
4
4.5 V
25
50
17
20
6V
29
60
20
MAX
UNIT
MHz
24
2V
54
165
245
205
4.5 V
16
33
49
41
6V
13
28
42
35
2V
56
125
185
155
4.5 V
16
25
37
31
6V
13
21
31
26
2V
29
75
110
95
4.5 V
9
15
22
19
6V
8
13
19
16
ns
ns
5.7 Operating Characteristics
TA = 25℃
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
TYP
35
UNIT
pF
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SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 6-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
50%
90%
VOH
90%
10%
50%
10%
tr(1)
(1)
VOH
Output
0V
tf(1)
Output
50%
(1)
VCC
90%
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
8
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7 Detailed Description
7.1 Overview
The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to
the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops
by tying J and K high.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS
(1)
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
H
H
L
X
X
X
L
H
H(1)
Q0
L
L
X
X
X
H(1)
H
H
↓
L
L
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
H
H
H
X
X
Toggle
Q0
Q0
This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its
inactive (high) level.
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
84088012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84088012A
SNJ54HC
112FK
8408801EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408801EA
SNJ54HC112J
Samples
8408801FA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408801FA
SNJ54HC112W
Samples
JM38510/65305BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65305BEA
Samples
M38510/65305BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65305BEA
Samples
SN54HC112J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC112J
Samples
SN74HC112D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC112
Samples
SN74HC112DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC112
Samples
SN74HC112DT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC112
Samples
SN74HC112N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC112N
Samples
SNJ54HC112FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
84088012A
SNJ54HC
112FK
SNJ54HC112J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408801EA
SNJ54HC112J
Samples
SNJ54HC112W
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408801FA
SNJ54HC112W
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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