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SN74HC4066
SCLS325J – MARCH 1996 – REVISED MARCH 2019
SN74HC4066 quadruple bilateral analog switch
1 Features
3 Description
•
•
•
•
•
•
•
•
The SN74HC4066 device is a silicon-gate CMOS
quadruple analog switch designed to handle both
analog and digital signals. Each switch permits
signals with amplitudes of up to 6 V (peak) to be
transmitted in either direction.
1
•
Wide Operating Voltage Range of 2 V to 6 V
Typical Switch Enable Time of 18 ns
Low Power Consumption, 20-µA Maximum ICC
Low Input Current of 1 µA Maximum
High Degree of Linearity
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Low On-State Impedance: 50-Ω Typical at
VCC = 6 V
Individual Switch Controls
Each switch section has its own enable input control
(C). A high-level voltage applied to C turns on the
associated switch section.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
2 Applications
•
•
•
•
•
•
•
•
Device Information(1)
Analog Signal Switching/Multiplexing:
– Signal Gating, Modulator, Squelch Control,
Demodulator, Chopper, Commutating Switch
Digital Signal Switching/Multiplexing
– Audio and Video Signal Routing
Transmission-Gate Logic Implementation
Analog-to-Digital and Digital-to-Analog Conversion
Digital Control of Frequency, Impedance, Phase,
and Analog-Signal Gain
Motor Speed Control
Battery Chargers
DC-DC Converter
PART NUMBER
PACKAGE
(PINS)
BODY SIZE (NOM)
SN74HC4066D
SOIC (14)
8.65 mm × 3.91 mm
SN74HC4066DB
SSOP (14)
6.20 mm × 5.30 mm
SN74HC4066PW
TSSOP (14)
5..00 mm × 4.40 mm
SN74HC4066N
PDIP (14)
19.30 mm × 6.35 mm
SN74HC4066NS
SO (14)
10.30 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Switch (Positive Logic)
A
VCC
VCC
B
C
One of Four Switches
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HC4066
SCLS325J – MARCH 1996 – REVISED MARCH 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (January 2019) to Revision J
•
Changed the MAX values for Isoff , Ison , and ICC in the Electrical Characteristics table........................................................... 5
Changes from Revision H (August 2016) to Revision I
•
Page
Page
Changed the Description of pins 8 through 12 in the Pin Functions table ............................................................................. 3
Changes from Revision G (July 2003) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Ordering Information table, see POA at the end of the datasheet............................................................................ 1
2
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5 Pin Configuration and Functions
D, DB, N, NS or PW Package
(Top View)
1A
1
14
VCC
1B
2
13
1C
2B
3
12
4C
2A
4
11
4A
2C
5
10
4B
3C
6
9
3B
GND
7
8
3A
No t to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1A
I/O
Switch 1 input/output
2
1B
I/O
Switch 1 output/input
3
2B
I/O
Switch 2 output/input
4
2A
I/O
Switch 2 input/output
5
2C
I
Switch 2 control
6
3C
I
Switch 3 control
7
GND
—
Ground
8
3A
I/O
Switch 3 input/output
9
3B
I/O
Switch 3 output/input
10
4B
I/O
Switch 4 output/input
11
4A
I/O
Switch 4 input/output
12
4C
I
Switch 4 control
Switch 1 control
13
1C
I
14
VCC
—
Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage (2)
II
Control-input diode current
II
I/O port diode current
On-state switch current
MIN
MAX
UNIT
–0.5
7
V
VI < 0 or VI > VCC
±20
mA
VI < 0 or VI/O > VCC
±20
mA
VI/O = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. CDM value for N
package only.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VI/O
I/O port voltage
High-level input voltage, control inputs
VIL
Low-level input voltage, control inputs
NOM
(2)
5
2
VCC = 2 V
VIH
MIN
VCC = 4.5 V
Input transition rise and fall time
TA
Operating free-air temperature
6
V
VCC
V
1.5
VCC
3.15
VCC
VCC = 6 V
4.2
VCC
VCC = 2 V
0
0.3
VCC = 4.5 V
0
0.9
VCC = 6 V
0
(2)
4
V
V
1.2
1000
VCC = 4.5 V
500
VCC = 6 V
(1)
UNIT
0
VCC = 2 V
∆t/∆v
MAX
ns
400
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application
report,Implications of Slow or Floating CMOS Inputs (SCBA004).
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
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6.4 Thermal Information
SN74HC4066
THERMAL METRIC
(1)
D
(SOIC)
DB
(SSOP)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
89.4
103.6
53.2
87.6
118.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.5
55.6
40.5
45.4
47.3
°C/W
RθJB
Junction-to-board thermal resistance
43.6
50.8
33.1
46.3
60.2
°C/W
ψJT
Junction-to-top characterization parameter
17.2
21
25.3
15.8
5.2
°C/W
ψJB
Junction-to-board characterization parameter
43.4
50.3
33
46
59.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40 to +85 °C unless otherwise specified.
PARAMETER
TEST CONDITIONS
TA = 25 C
ron
ron(p)
IT = –1 mA, VI = 0 to VCC,
VC = VIH (see Figure 2)
On-state switch resistance
VI = VCC or GND, VC = VIH,
IT = –1 mA
Peak on-state resistance
TA = 25 C
TA = –40 to +85
4.5 V
MIN
TYP
50
30
2V
320
TA = –40 to +85
TA = –40 to +85
Control input current
VC = 0 or VCC
Isoff
Off-state switch leakage current
VI = VCC or 0, VO = VCC or 0, TA = –40 to +85
VC = VIL (see Figure 3)
TA = 25 C
Ison
On-state switch leakage current
VI = VCC or 0, VC = VIH
(see Figure 4)
ICC
Supply current
VI = 0 or VCC, IO = 0
Ci
Input capacitance
Cf
Feed-through
capacitance
A to B
Co
Output capacitance
A or B
TA = 25 C
TA = –40 to +85
TA = 25 C
TA = –40 to +85
TA = 25 C
4.5 V
6V
6V
TA = –40 to +85
70
170
215
±0.1
±100
±1000
±5
±0.1
±5
6V
±0.1
20
6V
2
Ω
nA
µA
µA
µA
3
10
pF
10
VI = 0
5V
0.5
pF
9
pF
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Ω
9
5V
TA = 25 C
Copyright © 1996–2019, Texas Instruments Incorporated
UNIT
50
6V
TA = 25 C
85
106
6V
TA = 25 C
MAX
150
TA = 25 C
II
C
2V
TA = 25 C
TA = 25 C
A or B
VCC
5
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SCLS325J – MARCH 1996 – REVISED MARCH 2019
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6.6 Switching Characteristics
TA = –40 to +85 °C unless otherwise specified.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC
TA = 25°C
TA = –40 to +85
tPLH,
tPHL
Propagation
delay time
A or B
CL = 50 pF
(see Figure 5)
B or A
TA = 25°C
TA = –40 to +85
TA = 25°C
TA = –40 to +85
TA = 25°C
TA = –40 to +85
tPZH,
tPZL
Switch
turn-on time
C
RL = 1 kΩ,
CL = 50 pF
(see Figure 6)
A or B
TA = 25°C
TA = –40 to +85
TA = 25°C
TA = –40 to +85
TA = 25°C
TA = –40 to +85
tPLZ,
tPHZ
Switch
turn-off time
C
RL = 1 kΩ,
CL = 50 pF
(see Figure 6)
A or B
TA = 25°C
TA = –40 to +85
TA = 25°C
TA = –40 to +85
fI
Control input
frequency
Control
feed-through
noise
C
A or B
C
A or B
MIN
TYP
MAX
10
60
2V
UNIT
75
4
4.5 V
12
ns
15
3
6V
10
13
70
2V
180
225
21
4.5 V
36
ns
45
6V
18
31
50
200
38
2V
250
25
4.5 V
40
ns
50
22
6V
34
43
CL = 15 pF,
RL = 1 kΩ,
VC = VCC or
GND,
VO = VCC / 2
(see Figure 7)
TA = 25°C
2V
15
TA = 25°C
4.5 V
30
TA = 25°C
6V
30
CL = 50 pF,
Rin = RL = 600
Ω,
VC = VCC or
GND,
fin = 1 MHz
(see Figure 8)
TA = 25°C
4.5 V
15
TA = 25°C
6V
20
MHz
mV
(rms)
6.7 Operating Characteristics
VCC = 4.5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
6
UNIT
CL = 50 pF,
f = 1 MHz
45
pF
CL = 50 pF,
VC = VCC
RL = 600 Ω,
(see Figure 9)
30
MHz
Crosstalk between any switches (2)
CL = 10 pF,
fin = 1 MHz
RL = 50 Ω,
(see Figure 10)
45
dB
Feed through, switch off, A to B or B to A (2)
CL = 50 pF,
fin = 1 MHz
RL = 600 Ω,
(see Figure 11)
42
dB
Amplitude distortion rate, A to B or B to A
CL = 50 pF,
fin = 1 kHz
RL = 10 kΩ,
(see Figure 12)
0.05%
Minimum through bandwidth, A to B or B to A
(1)
(2)
TYP
(1)
[20 log (VO / VI)] = –3 dB
Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave.
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tPLH (ns)
6.8 Typical Characteristics
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
25 oC and CL=50 pF
2
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
6
D001
Figure 1. tPLH vs VCC
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7 Parameter Measurement Information
VCC
VC = VIH
V CC
VI = VCC
VO
(ON)
GND
+
r on =
V –O
10 –3
Ω
1.0 mA
V
V I–O
Figure 2. ON-State Resistance Test Circuit
VCC
VC = VIL
VCC
A
A
B
(OFF)
GND
VS = VA – VB
CONDITION 1: VA = 0, VB = VCC
CONDITION 2: VA = VCC, VB = 0
Figure 3. OFF-State Switch Leakage-Current Test Circuit
VCC
VC = VIH
VCC
A
A
VCC
B
(ON)
GND
Open
VA = VCC TO GND
Figure 4. ON-State Leakage-Current Test Circuit
8
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Parameter Measurement Information (continued)
VCC
VC = VIH
VCC
VO
VI
50 Ω
50 pF
GND
TEST CIRCUIT
tr
VI
A or B
tf
90%
50%
10%
tPLH
VO
B or A
VCC
90%
50%
10%
0V
tPHL
VOH
50%
50%
VOL
VOLTAGE WAVEFORMS
Figure 5. Propagation Delay Time, Signal Input to Signal Output
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Parameter Measurement Information (continued)
VCC
50 Ω
VC
RL
VO 1 kΩ
VCC
VI
S2
S1
TEST
S1
S2
tPZL
tPZH
tPLZ
tPHZ
GND
VCC
GND
VCC
VCC
GND
VCC
GND
CL
50 pF
GND
TEST CIRCUIT
VCC
VCC
VC
50%
50%
0V
0V
tPZH
tPZL
VOH
VOH
VO
50%
50%
VOL
VOL
(tPZL, tPZH)
VCC
VCC
VC
50%
50%
0V
0V
tPHZ
tPLZ
VOH
VOH
VO
10%
VOL
90%
VOL
(tPLZ, tPHZ)
VOLTAGE WAVEFORMS
Figure 6. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VCC
VCC
50 Ω
VI = VCC
VC
VC
0V
VCC
GND
VO
RL
1 kΩ
CL
15 pF
VCC/2
Figure 7. Control-Input Frequency
10
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Parameter Measurement Information (continued)
VCC
50 Ω
tr
VC
VCC
VCC
VI
GND
Rin
600 Ω
RL
600 Ω
VCC/2
90% 90%
VC
VO
10%
0V
CL
50 pF
tf
10%
(f = 1 MHz)
tr = tf = 6 ns
VCC/2
Figure 8. Control Feed-Through Noise
VCC
VC = VCC
0.1 µF
fin
VCC
(ON)
VI
VI
VO
GND
50 Ω
RL
600 Ω
CL
50 pF
(VI = 0 dBm at f = 1 MHz)
VCC/2
Figure 9. Minimum Through Bandwidth
VCC
VC = VCC
50 Ω
VCC
(ON)
VI
fin
0.1 µF Rin
600 Ω
VO1
GND
RL
600 Ω
CL
50 pF
VCC/2
VI
VCC
VC = GND
(VI = 0 dBm at f = 1 MHz)
VCC
(OFF)
Rin
600 Ω
GND
VO2
RL
600 Ω
CL
50 pF
VCC/2
Figure 10. Crosstalk Between Any Two Switches
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Parameter Measurement Information (continued)
VCC
VC = GND
0.1 µF
50 Ω
VCC
(OFF)
VI
fin
Rin
600 Ω
VI
VO
RL
600 Ω
GND
VCC/2
CL
50 pF
(VI = 0 dBm at f = 1 MHz)
VCC/2
Figure 11. Feed Through, Switch OFF
VCC
VC = VCC
fin
VI
10 µF
VCC
(ON)
GND
VI
VO
RL
10 kΩ
CL
50 pF
(VI = 0 dBm at f = 1 kHz)
VCC/2
Figure 12. Amplitude-Distortion Rate
12
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8 Detailed Description
8.1 Overview
The SN74HC4066 device is a silicon-gate CMOS quadruple analog switch designed for 2-V to 6-V VCC
operation. It is designed to handle both analog and digital signals. Each switch permits signals with amplitudes of
up to 6 V (peak) to be transmitted in either direction. A high-level voltage applied to the control pin C enables the
respective switch to begin propagating signals across the device.
8.2 Functional Block Diagram
A
VCC
VCC
B
C
One of Four Switches
Copyright © 2016, Texas Instruments Incorporated
Figure 13. Logic Diagram, Each Switch
(Positive Logic)
8.3 Feature Description
Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the
associated switch section, with typically 18 ns of switch enable time. The SN74HC4066 has a wide operating
voltage range of 2 V to 6 V. It has low power consumption, with 20-µA maximum ICC and a low on-state
impedance of 50 Ω. It also has low crosstalk between switches to minimize noise.
8.4 Device Functional Modes
Table 1 lists the functions for the SN74HC4066 device.
Table 1. Function Table
(Each Switch)
INPUT
CONTROL
(C)
SWITCH
L
OFF
H
ON
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HC4066 can be used in any situation where an dual SPST switch would be used and a solid-state,
voltage controlled version is preferred.
9.2 Typical Application
Vcc= 1.65V to 5.5V
0.1 PF
1C
1B
Microcontroller
Or
System Logic
Microcontroller
Or
System Logic
1A
2A
2B
2C
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Figure 14. tPZH vs VCC
9.2.1 Design Requirements
The SN74HC4066 allows ON/OFF control of analog and digital signals with a digital control signal. All input
signals should remain between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommended Output Conditions:
– On-state switch current should not exceed ±25 mA.
14
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Typical Application (continued)
9.2.3 Application Curve
70
25 oC and CL = 50 pF
65
60
55
tPZH (ns)
50
45
40
35
30
25
20
15
2
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
6
D001
Figure 15. tPZH vs VCC
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF bypass capacitor. If there are multiple pins labeled VCC, then a 0.01-µF or
0.022-µF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, TI recommends a 0.1-µF
bypass capacitor for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self-inductance of the
trace — resulting in the reflection.
NOTE
Not all PCB traces can be straight, and so they will have to turn corners. Figure 16 shows
progressively better techniques of rounding corners. Only the last example maintains
constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 16. Trace Example
16
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Copyright © 1996–2019, Texas Instruments Incorporated
Product Folder Links: SN74HC4066
SN74HC4066
www.ti.com
SCLS325J – MARCH 1996 – REVISED MARCH 2019
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 1996–2019, Texas Instruments Incorporated
Product Folder Links: SN74HC4066
17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC4066D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC4066N
SN74HC4066NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
SN74HC4066PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC4066
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Mar-2019
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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