SN74HC688N

SN54HC688, SN74HC688 SCLS010F – DECEMBER 1982 – REVISED MAY 2022 SN54HC688, SN74HC688 8-Bit Identity Comparators 1 Features 2 Description • • • • • • • These identity comparators perform comparisons of two 8-bit binary or BCD words. An output-enable (OE) input may be used to force the output to the high level. Wide operating voltage range of 2 V to 6 V High-current outputs drive up to 10 LSTTL loads Low power consumption, 80-μA max ICC Typical tpd = 14 ns ±4-mA output drive at 5 V Low input current of 1 μA max Compare two 8-bit words Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC688DW SOIC (20) 12.80 mm × 7.50 mm SN74HC688N PDIP (20) 25.40 mm × 6.35 mm SN74HC688PWR TSSOP (20) 6.50 mm × 4.40 mm SN54HC688J CDIP (20) 26.92 mm × 6.92 mm SNJ54HC688FK LCCC (20) 8.89 mm × 8.45 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings ....................................... 4 5.2 Recommended Operating Conditions(1) .................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics ...........................................5 5.6 Operating Characteristics........................................... 5 6 Parameter Measurement Information............................ 6 7 Detailed Description........................................................7 7.1 Overview..................................................................... 7 7.2 Functional Block Diagram........................................... 7 7.3 Device Functional Modes............................................7 8 Power Supply Recommendations..................................8 9 Layout...............................................................................8 9.1 Layout Guidelines....................................................... 8 10 Device and Documentation Support............................9 10.1 Receiving Notification of Documentation Updates....9 10.2 Support Resources................................................... 9 10.3 Trademarks............................................................... 9 10.4 Electrostatic Discharge Caution................................9 10.5 Glossary....................................................................9 11 Mechanical, Packaging, and Orderable Information...................................................................... 9 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2022) to Revision F (May 2022) Page • Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, N was 69 is now 84.6, PW was 83 is now 131.8.................................................................................................................................... 4 Changes from Revision D (August 2003) to Revision E (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC688 SN74HC688 SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 4 Pin Configuration and Functions J, DW, N or PW package 20-Pin CDIP, SOIC, PDIP, TSSOP Top View FK Package 20-Pin LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC688 SN74HC688 3 SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range current(2) MIN MAX –0.5 7 UNIT V IIK Input clamp VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 ℃ 150 ℃ Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range (1) (2) –65 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions(1) SN54HC688 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V NOM MAX 2 5 6 Low-level input voltage VI Input voltage VO Output voltage TA (1) MAX 2 5 6 3.15 3.15 4.2 4.2 VCC = 4.5 V 0 0.5 0.5 1.35 1.35 0 V VCC 0 VCC V VCC V 1000 VCC = 4.5 V 500 500 VCC = 6 V 400 400 –55 V 1.8 VCC 1000 Operating free-air temperature UNIT V 1.8 0 VCC = 2 V Input transition (rise and fall) time NOM 1.5 VCC = 6 V tt MIN 1.5 VCC = 2 V VIL SN74HC688 MIN 125 –40 85 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5.3 Thermal Information THERMAL METRIC N (PDIP) PW (TSSOP) 20 PINS 20 PINS 20 PINS UNIT 109.1 84.6 131.8 °C/W RθJA Junction-to-ambient thermal resistance(1) RθJC(top) Junction-to-case (top) thermal resistance 76 72.5 72.2 °C/W RθJB Junction-to-board thermal resistance 77.6 65.3 82.8 °C/W ψJT Junction-to-top characterization parameter 51.5 55.3 21.5 °C/W ψJB Junction-to-board characterization parameter 77.1 65.2 82.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) 4 DW (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC688 SN74HC688 SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 μA VOH 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 VI = VCC or 0, MAX MIN MAX UNIT V 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 μA 10 10 10 pF IOL = 5.2 mA VI = VCC or 0 MIN IOL = 20 μA VI = VIH or VIL II MAX SN74HC688 TYP IOH = –5.2 mA ICC SN54HC688 MIN VI = VIH or VIL IOH = –4 mA VOL TA = 25°C VCC IO = 0 6V Ci 2 V to 6 V 3 V 5.5 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement Information) PARAMETER FROM (INPUT) TO (OUTPUT) VCC P or Q P=Q tpd OE tt P=Q Any TA = 25°C MIN SN54HC688 MIN SN74HC688 TYP MAX MAX MIN MAX 2V 113 210 313 265 4.5 V 30 42 63 53 6V 24 36 53 45 2V 66 120 179 151 4.5 V 16 24 36 30 6V 14 20 30 26 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns 5.6 Operating Characteristics TA = 25℃ PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 40 UNIT pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC688 SN74HC688 5 SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. VCC Test Point S1 RL From Output Under Test CL(1) S2 (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for 3-State Outputs VCC Input 50% VCC Output Control 50% 50% 50% 0V 0V tPHL(1) tPLH(1) tPZL(3) VOH Output 50% VOL tPHL (1) tPLH 50% 50% 10% VOL (1) tPZH VOH Output § 9CC Output Waveform 1 S1 at VLOAD(1) 50% Output Waveform 2 S1 at GND(2) 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. tPLZ(4) (3) tPHZ (4) 90% VOH 50% §0V (1) S1 = CLOSED; S2 = OPEN. (2) S1 = OPEN; s2 = CLOSED. (3) tPLZ and tPHZ are the same as tdis. (4) tPZL and tPZH are the same as ten. Figure 6-2. Voltage Waveforms, Propagation Delays for Standard CMOS Inputs Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Propagation Delays 90% VCC 90% Input 10% 10% tr(1) 0V tf(1) 90% VOH 90% Output 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-4. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Inputs 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC688 SN74HC688 SN54HC688, SN74HC688 www.ti.com SCLS010F – DECEMBER 1982 – REVISED MAY 2022 7 Detailed Description 7.1 Overview These identity comparators perform comparisons of two 8-bit binary or BCD words. An output-enable (OE) input may be used to force the output to the high level. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Function Table INPUTS DATA P, Q OE OUTPUT P=Q P=Q L L P>Q X H P