SN54HC7032, SN74HC7032
SCLS036F – MARCH 1984 – REVISED JUNE 2021
SN74HC7032 Quadruple 2-Input OR Gates with Schmitt-Trigger Inputs
1 Features
3 Description
•
•
•
•
•
•
This device contains four independent 2-input OR
Gates with Schmitt-trigger inputs. Each gate performs
the Boolean function Y = A + B in positive logic.
Wide Operating Voltage Range: 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Maximum ICC
Operation from very slow input transitions
±4-mA Output Drive at 5 V
Low Input Current of 1 µA
2 Applications
•
•
Device Information1
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC7032N
PDIP (14)
19.30 mm × 6.40 mm
SN74HC7032D
SOIC (14)
8.70 mm × 3.90 mm
Use fewer inputs to monitor error signals
Combine active-low enable signals
1A
1
14
1B
2
13
1Y
3
12
2A
4
11
2B
5
10
2Y
6
9
GND
7
8
VCC
4B
4A
4Y
3B
3A
3Y
Functional pinout of the SN74HC7032
1
#none#
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Operating Characteristics .......................................... 4
6.5 Thermal Information ...................................................4
6.6 Electrical Characteristics ............................................5
6.7 Switching Characteristics ..........................................6
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Related Links.......................................................... 14
12.3 Support Resources................................................. 14
12.4 Trademarks............................................................. 14
12.5 Electrostatic Discharge Caution..............................14
12.6 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2004) to Revision F (June 2019)
Page
• Updated to new data sheet standards................................................................................................................ 1
• Updated the number format for tables, figures, and cross-references throughout the document...................... 1
• RθJA increased for the D (86 to 133.6 ℃/W) and decreased for the N package (80 to 61.4 ℃/W)................... 4
2
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5 Pin Configuration and Functions
1A
1
14
VCC
1B
2
13
4B
1Y
2A
3
12
4
11
4A
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Figure 5-1. D or N Package
14-Pin SOIC or PDIP
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A
1
Input
Channel 1, Input A
1B
2
Input
Channel 1, Input B
1Y
3
Output
2A
4
Input
Channel 2, Input A
2B
5
Input
Channel 2, Input B
2Y
6
Output
GND
7
—
3Y
8
Output
3A
9
Input
Channel 3, Input A
3B
10
Input
Channel 3, Input B
4Y
11
Output
4A
12
Input
Channel 4, Input A
4B
13
Input
Channel 4, Input B
VCC
14
—
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Channel 1, Output Y
Channel 2, Output Y
Ground
Channel 3, Output Y
Channel 4, Output Y
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC +
0.5 V
IOK
Output clamp current(2)
VO < –0.5 V or VO > VCC +
0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±20
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature(3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Operating free-air temperature
–40
85
°C
SN74HC00
6.4 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
VCC
MIN
2 V to 6 V
TYP
MAX UNIT
20
pF
6.5 Thermal Information
SN74HC7032
THERMAL METRIC(1)
4
N (PDIP)
D (SOIC)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
61.4
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.2
89.0
°C/W
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SN74HC7032
THERMAL METRIC(1)
N (PDIP)
D (SOIC)
UNIT
14 PINS
14 PINS
RθJB
Junction-to-board thermal resistance
41.2
89.5
°C/W
ΨJT
Junction-to-top characterization parameter
28.8
45.5
°C/W
ΨJB
Junction-to-board characterization parameter
40.9
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
VT+
VT-
ΔVT
VOH
VOL
TEST CONDITIONS
2V
Positive
switching
threshold
Hysteresis (VT+ VT-)
VI = VIH
or VIL
Low-level output VI = VIH
voltage
or VIL
IOH = -20 µA
25°C
TYP
MAX
MIN
TYP
MAX
0.7
1.2
1.5
0.7
1.5
2.5
3.15
1.55
3.15
6V
2.1
3.3
4.2
2.1
4.2
2V
0.3
0.6
1
0.3
1
4.5 V
0.9
1.6
2.45
0.9
2.45
6V
1.2
2
3.2
1.2
3.2
2V
0.2
0.6
1.2
0.2
1.2
4.5 V
0.4
0.9
2.1
0.4
2.1
6V
0.5
1.3
2.5
0.5
2.5
2V
1.9
1.998
1.9
4.5 V
4.4
4.499
4.4
6V
5.9
5.999
5.9
IOH = -4 mA
4.5 V
3.98
4.3
3.84
IOH = -5.2 mA
6V
5.48
5.8
5.34
IOL = 20 µA
UNIT
-40°C to 85°C
MIN
1.55
4.5 V
Negative
switching
threshold
High-level
output voltage
VCC
V
V
V
V
2V
0.002
0.1
0.1
4.5 V
0.001
0.1
0.1
6V
0.001
0.1
0.1
IOL = 4 mA
4.5 V
0.17
0.26
0.33
IOL = 5.2 mA
6V
0.15
0.26
0.33
±0.1
±100
±1000
nA
2
20
µA
10
10
pF
II
Input leakage
current
VI = VCC or 0
6V
ICC
Supply current
VI = VCC
or 0
6V
Ci
Input
capacitance
VI = VCC or 0
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2 V to 6 V
3
V
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
tpd
Propagation delay
tt
A or B
Y
Transition-time
Any
UNIT
–40°C to 85°C
TYP
MAX
2V
60
130
MIN
TYP
MAX
163
4.5 V
18
26
33
6V
14
22
28
2V
28
75
95
4.5 V
8
15
19
6V
6
13
16
ns
ns
6.8 Typical Characteristics
TA = 25°C
6
3
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
2.4
2.1
1.8
5.4
VOH, Output High Voltage (V)
VOL, Output Low Voltage (V)
2.7
1.5
1.2
0.9
0.6
0.3
3.6
3
2.4
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
1.8
1.2
0
0
2.5
5
7.5 10 12.5 15 17.5 20
IOL, Output Low Current (mA)
22.5
25
Figure 6-1. Typical output low voltage versus sink
current across common supply values
0
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 6-3. Typical supply current versus input
voltage across common supply values (2 V to 3.3
V)
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6
9
12
15
18
21
24
IOH, Output High Current (mA)
27
30
Figure 6-2. Typical output high voltage versus
source current across common supply values
0.2
0.18
ICC ± Supply Current (mA)
4.2
0.6
0
6
4.8
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 6-4. Typical supply current versus input
voltage across common supply values (4.5 V to 6
V)
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7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
The outputs are measured one at a time, with one input transition per measurement.
Test
Point
90%
VCC
90%
Input
10%
10%
tr(1)
From Output
Under Test
CL(1)
0V
tf(1)
90%
VOH
90%
Output
10%
A.
10%
tr(1)
CL= 50 pF and includes probe and jig capacitance.
A.
Figure 7-1. Load Circuit
tf(1)
VOL
tt is the greater of tr and tf.
Figure 7-2. Voltage Waveforms Transition Times
VCC
Input
50%
50%
0V
tPLH
(1)
tPHL
(1)
VOH
Output
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
A.
The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A + B in positive logic.
8.2 Functional Block Diagram
A
Y
B
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings table must be followed
at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics table. The worst case resistance is calculated with the
maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current,
given in the Electrical Characteristics table, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs slowly will also increase dynamic current consumption of the device. For additional information regarding
Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Section 6.1 table can cause damage to the device.
The input negative-voltage and output voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
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VCC
Device
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, three 2-input OR gates are combined to produce a 4-input OR gate function as shown in
Figure 9-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
The SN74HC7032 is used to directly control the Enable pin of a fan driver. The fan driver requires only one
input signal to be HIGH before being enabled, and should be disabled in the event that all signals go LOW. The
4-input OR gate function combines the four individual overheat signals into a single active-high enable signal.
Temperature sensors can often be spread throughout a system rather than being in a centralized location. This
would mean longer length traces or wires to pass signals through leading to slower edge transitions. This makes
the SN74HC7032 ideal for the application since it has Schmitt-trigger inputs that do not have input transition rate
requirements.
9.2 Typical Application
Device 1
Overheat
Device 2
Overheat
Fan
Driver
EN
Device 3
Overheat
Device 4
Overheat
Figure 9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the maximum static supply current, ICC,
listed in Electrical Characteristics and any transient current required for switching.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HC7032 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The SN74HC7032 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed
50 pF.
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The SN74HC7032 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOL. When outputting in the high state, the output
voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross to be considered a logic LOW, and to be considered a logic HIGH. Do not exceed the
maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HC7032, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HC7032 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
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9.2.3 Application Curves
Device 1
Device 2
Device 3
Device 4
EN
Figure 9-2. Application timing diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
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11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
Figure 11-1. Example layout for the SN74HC7032
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC7032
Click here
Click here
Click here
Click here
Click here
SN74HC7032
Click here
Click here
Click here
Click here
Click here
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
14
This glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2021 Texas Instruments Incorporated
www.ti.com
SN54HC7032, SN74HC7032
SCLS036F – MARCH 1984 – REVISED JUNE 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HC7032D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC7032
SN74HC7032DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC7032
SN74HC7032N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC7032N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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