Product
Folder
Order
Now
Tools &
Software
Technical
Documents
参考資料
Support &
Community
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
SN74HCS4075-Q1 車載用、 シュミット・トリガ入力を搭載したトリプル
3 入力 OR ゲート
1 特長
•
1
•
•
•
•
2 アプリケーション
車載アプリケーション用に AEC-Q100 認定済み
– デバイス温度グレード 1: -40°C～+125°C、TA
– デバイス HBM ESD 分類レベル 2
– デバイス CDM ESD 分類レベル C6
広い動作電圧範囲: 2V～6V
シュミット・トリガ入力により低速またはノイズ
の多い入力信号に対応
低消費電力
– ICC：100nA (標準値)
– 入力リーク電流：±100nA (標準値)
5V で ±7.8mA の出力駆動能力
•
•
少ない入力によりエラー信号を監視
アクティブ LOW のイネーブル信号の結合
3 概要
このデバイスには、3 つの独立した 3 入力 OR ゲートと、
シュミット・トリガ入力が内蔵されています。各ゲートはブー
ル関数 Y = A + B + C を正論理で実行します。
製品情報(1)
型番
パッケージ
本体サイズ（公称）
SN74HCS4075QDRQ
1
SOIC (14)
8.70mm×3.90mm
SN74HCS4075QPWR
Q1
TSSOP (14)
5.00mm×4.40mm
(1) 利用可能なすべてのパッケージについては、このデータシートの末
尾にある注文情報を参照してください。
シュミットトリガ入力の利点
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Voltage
Output
Voltage
Time
Current
Response
Waveforms
Time
Time
Input Voltage
Output
Schmitt-trigger
CMOS Input
Time
Time
Current
Response
Waveforms
Supply Current
Standard
CMOS Input
Supply Current
Input Voltage
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
Time
1
英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当する正式な英語版の最新情報は、www.ti.comで閲覧でき、その内
容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
English Data Sheet: SCLS768
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.ti.com
目次
1
2
3
4
5
6
7
8
特長 ..........................................................................
アプリケーション .........................................................
概要 ..........................................................................
改訂履歴...................................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 デバイスおよびドキュメントのサポート ....................... 14
12.1
12.2
12.3
12.4
12.5
12.6
ドキュメントのサポート ..............................................
関連リンク ...............................................................
コミュニティ・リソース ................................................
商標 .......................................................................
静電気放電に関する注意事項 ................................
Glossary ................................................................
14
14
14
14
14
14
13 メカニカル、パッケージ、および注文情報 ................. 14
4 改訂履歴
2019年
年8月
月発行のものから更新
Page
•
データシートに D パッケージを 追加 ......................................................................................................................................... 1
•
Deleted "ICC" and "output" from "Continuous current through VCC or GND" row for clarity .................................................... 4
2
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.ti.com
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
D or PW Package
14-Pin SOIC or TSSOP
Top View
2A
1
14
2B
2
13
1A
3
12
1B
4
11
1C
5
10
1Y
6
9
GND
7
8
VCC
3C
3B
3A
3Y
2Y
2C
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
2A
1
Input
Channel 2, Input A
2B
2
Input
Channel 2, Input B
1A
3
Input
Channel 1, Input A
1B
4
Input
Channel 1, Input B
1C
5
Input
Channel 1, Input C
1Y
6
Output
GND
7
—
2C
8
Input
2Y
9
Output
Channel 2, Output Y
3Y
10
Output
Channel 3, Output Y
3A
11
Input
Channel 3, Input A
3B
12
Input
Channel 3, Input B
3C
13
Input
Channel 3, Input C
VCC
14
—
Copyright © 2019, Texas Instruments Incorporated
Channel 1, Output Y
Ground
Channel 2, Input C
Positive Supply
3
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
V
IIK
Input clamp current (2)
VI < –0.5 or VI > VCC +
0.5
±20
mA
IOK
Output clamp current (2)
VO < –0.5 or VO > VCC +
0.5
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature (3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Do not exceed the absolute
maximum voltage supply rating.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
HBM ESD Classification Level 2
UNIT
(1)
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±4000
V
±1500
AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
Δt/Δv
Input transition rise and fall rate
TA
Ambient temperature
VCC
Unlimited
–40
125
V
ns/V
°C
6.4 Thermal Information
SN74HCS4075-Q1
THERMAL METRIC
PW (TSSOP)
D (SOIC)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
151.7
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.4
89.0
°C/W
RθJB
Junction-to-board thermal resistance
94.7
89.5
°C/W
ΨJT
Junction-to-top characterization parameter
25.2
45.5
°C/W
ΨJB
Junction-to-board characterization parameter
94.1
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
4
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.tij.co.jp
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
6.5 Electrical Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
VOH
TEST CONDITIONS
VCC
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
High-level output voltage
VI = VIH or VIL
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
IOH = -6 mA
4.5 V
IOH = -7.8 mA
6V
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
4.5 V
IOL = 7.8 mA
VCC – 0.1
V
V
V
VCC – 0.002
4
4.3
5.4
5.75
V
0.002
0.1
0.18
0.30
VOL
Low-level output voltage
VI = VIH or VIL
6V
0.22
0.33
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
Cpd
Power dissipation capacitance
per gate
2 V to 6 V
No load
2 V to 6 V
10
V
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). See the
Parameter Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2V
tpd
tt
Propagation delay
Transition-time
Copyright © 2019, Texas Instruments Incorporated
A or B or C
Y
Y
MIN
TYP
MAX
13
32
4.5 V
6
15
6V
5
12
2V
9
17
4.5 V
5
8
6V
4
7
UNIT
ns
ns
5
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.tij.co.jp
6.7 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
0
図 1. Output driver resistance in Low state
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
図 2. Output driver resistance in High state
0.2
0.18
2.5
3.5
図 3. Typical supply current versus input voltage across
common supply values (2 V to 3.3 V)
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
図 4. Typical supply current versus input voltage across
common supply values (4.5 V to 6 V)
7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
The outputs are measured one at a time, with one input transition per measurement.
Test
Point
90%
VCC
90%
Input
10%
10%
tr(1)
From Output
Under Test
CL(1)
0V
tf(1)
90%
VOH
90%
Output
10%
CL= 50 pF and includes probe and jig capacitance.
図 5. Load Circuit
6
10%
tr(1)
tf(1)
VOL
図 6. Voltage Waveforms
Transition Times
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.tij.co.jp
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
Parameter Measurement Information (continued)
VCC
Input
50%
50%
0V
tPLH
(1)
tPHL
(1)
VOH
Output
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
The maximum between tPLH and TPHL is used for tpd.
図 7. Voltage Waveforms
Propagation Delays
Copyright © 2019, Texas Instruments Incorporated
7
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.tij.co.jp
8 Detailed Description
8.1 Overview
This device contains three independent 3-input OR Gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A + B + C in positive logic.
8.2 Functional Block Diagram
One of Three Channels
xA
xB
xY
xC
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 図 8.
注意
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
8
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.tij.co.jp
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
Feature Description (continued)
VCC
Device
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
図 8. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
表 1. Function Table
INPUTS
Copyright © 2019, Texas Instruments Incorporated
OUTPUT
A
B
C
Y
L
L
L
L
H
X
X
H
X
H
X
H
X
X
H
H
9
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.tij.co.jp
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HCS4075-Q1 includes three 3-input OR gates with Schmitt-trigger inputs. These 3-input OR gates
work independently, but can be combined to get up to a 7-input OR gate. It can be used with all three inputs
active, or one input can be disabled by directly connecting it to ground to turn the device into a 2-input OR gate.
The SN74HCS4075-Q1 is used to directly control the Enable pin of a fan driver. The fan driver requires only one
input signal to be HIGH before being enabled, and should be disabled in the event that all signals go LOW. The
3-input OR gate function combines the three individual overheat signals into a single active-high enable signal.
Temperature sensors can often be spread throughout a system rather than being in a centralized location. This
would mean longer length traces or wires to pass signals through leading to slower edge transitions. This makes
the SN74HCS4075-Q1 ideal for the application since it has Schmitt-trigger inputs that do not have input transition
rate requirements.
9.2 Typical Application
Device 1
Overheat
Fan
Driver
Device 2
Overheat
EN
Device 3
Overheat
図 9. Typical application block diagram
9.2.1 Design Requirements
• All signals in the system operate at 5 V
• The fan driver should be enabled if any one or more of these conditions apply:
– Device 1 overheats
– Device 2 overheats
– Device 3 overheats
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS4075-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
10
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.tij.co.jp
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
Typical Application (continued)
The SN74HCS4075-Q1 can drive a load with a total capacitance less than or equal to 50 pF connected to a
high-impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can
be applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
注意
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS4075-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS4075-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics. The plots in and provide a
typical relationship between output voltage and current for this device.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS4075-Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
Copyright © 2019, Texas Instruments Incorporated
11
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.tij.co.jp
Typical Application (continued)
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Device 1
Device 2
Device 3
EN
図 10. Application timing diagram
12
Copyright © 2019, Texas Instruments Incorporated
SN74HCS4075-Q1
www.tij.co.jp
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in 図
11.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
2A
1
14
2B
2
13
VCC Unused inputs
tied to VCC
3C
1A
3
12
3B
1B
4
11
3A
1C
5
10
3Y
1Y
6
9
2Y
GND
7
8
2C
Unused output
left floating
図 11. Example layout for the SN74HCS4075-Q1
Copyright © 2019, Texas Instruments Incorporated
13
SN74HCS4075-Q1
JAJSHW0A – AUGUST 2019 – REVISED OCTOBER 2019
www.tij.co.jp
12 デバイスおよびドキュメントのサポート
12.1 ドキュメントのサポート
12.1.1 関連資料
関連資料については、以下を参照してください。
• 『HCMOS Design Considerations』 (英語)
• 『CMOS Power Consumption and Cpd Calculation』 (英語)
• 『Designing With Logic』 (英語)
12.2 関連リンク
次の表に、クイック・アクセス・リンクを示します。カテゴリには、技術資料、サポートおよびコミュニティ・リソース、ツールとソフ
トウェア、およびサンプル注文またはご購入へのクイック・アクセスが含まれます。
12.3 コミュニティ・リソース
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商標
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静電気放電に関する注意事項
これらのデバイスは、限定的なESD（静電破壊）保護機能を内 蔵しています。保存時または取り扱い時は、MOSゲートに対す る静電破壊を防
止するために、リード線同士をショートさせて おくか、デバイスを導電フォームに入れる必要があります。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 メカニカル、パッケージ、および注文情報
以降のページには、メカニカル、パッケージ、および注文に関する情報が記載されています。この情報は、そのデバイスに
ついて利用可能な最新のデータです。このデータは予告なく変更されることがあり、ドキュメントが改訂される場合もありま
す。本データシートのブラウザ版を使用されている場合は、画面左側の説明をご覧ください。
14
Copyright © 2019, Texas Instruments Incorporated
重要なお知らせと免責事項
TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種
アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対す
る適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。
これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選
定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリ
ティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される
可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に
許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与さ
れている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI および
その代理人を完全に補償するものとし、TI は一切の責任を拒否します。
TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供
する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意
味するものではありません。IMPORTANT NOTICE
Copyright © 2020, Texas Instruments Incorporated
日本語版 日本テキサス・インスツルメンツ株式会社
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HCS4075QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS4075Q
SN74HCS4075QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC4075Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
