SN74HCS595
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
SN74HCS595 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output
Registers
1 Features
3 Description
•
•
The SN74HCS595 device contains an 8-bit, serialin, parallel-out shift register that feeds an 8-bit
D-type storage register. All inputs include Schmitttrigger architecture, eliminating any erroneous data
outputs due to slow-edged or noisy input signals. The
storage register has parallel 3-state outputs. Separate
clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear
(SRCLR) input, serial (SER) input, and a serial output
(QH') for cascading. When the output-enable (OE)
input is high, the storage register outputs are in a
high-impedance state. Internal register data and serial
output (QH') are not impacted by the operation of the
OE input.
2 Applications
Output expansion
LED matrix control
7-segment display control
8-bit data storage
Device Information
PART NUMBER
TSSOP (16)
5.00 mm x 4.40 mm
SOIC (16)
9.90 mm x 3.90 mm
SN74HCS595BQB
WQFN (16)
3.60 mm x 2.60 mm
SN74HCS595DYY
SOT-23-THN 4.20 mm x 2.00 mm
(16)
Input
Voltage
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Time
Time
Voltage
Time
Input Voltage
Output
Response
Waveforms
Time
Current
Schmitt-trigger
CMOS Input
Supports Slow Inputs
Time
Output
Response
Waveforms
Supply Current
Standard
CMOS Input
For all available packages, see the orderable addendum at
the end of the data sheet.
Noise Rejection
Input Voltage
BODY SIZE (NOM)
SN74HCS595D
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
PACKAGE(1)
SN74HCS595PW
(1)
Supply Current
•
•
•
•
Voltage
•
•
Current
•
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to
+125°C, TA
Time
Benefits of Schmitt-trigger inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Characteristics ................................................5
6.7 Switching Characteristics ...........................................6
6.8 Operating Characteristics .......................................... 7
6.9 Typical Characteristics................................................ 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Functional Block Diagram......................................... 10
8.2 Feature Description...................................................10
8.3 Device Functional Modes..........................................11
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Receiving Notification of Documentation Updates..17
12.3 Support Resources................................................. 17
12.4 Trademarks............................................................. 17
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2020) to Revision A (October 2020)
Page
• BQB and D packages changed to Active status................................................................................................. 1
• Datasheet status changed to Production Data................................................................................................... 1
Changes from Revision A (October 2020) to Revision B (May 2021)
Page
• Added DYY Package to Device Information Table............................................................................................. 1
• Added DYY Package pinout diagram and information to Pin Configuration and Functions............................... 3
• Added DYY Package to Thermal Information table............................................................................................ 4
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
5 Pin Configuration and Functions
QB
VCC
1
16
QB
1
16
VCC
QC
2
QA
QC
2
15
QA
QD
QE
3
15
14
QD
3
13
QE
4
14
13
SER
4
SER
OE
QF
5
12
RCLK
QF
5
QG
QH
6
11
SRCLK
QG
6
11
SRCLK
7
8
10
SRCLR
QH¶
QH
7
10
SRCLR
GND
9
PAD
8
12
OE
RCLK
9
GND QH`
D, PW, or DYY Package
16-Pin SOIC, TSSOP, or SOT-23
Top View
BQB Package
16-Pin WQFN
Transparent Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
QB
1
Output
QC
2
Output
QC output
QD
3
Output
QD output
QB output
QE
4
Output
QE output
QF
5
Output
QF output
QG
6
Output
QG output
QH
7
Output
QH output
GND
8
—
QH'
9
Output
Ground
SRCLR
10
Input
Shift register clear, active low
SRCLK
11
Input
Shift register clock, rising edge triggered
RCLK
12
Input
Output register clock, rising edge triggered
OE
13
Input
Output Enable, active low
Serial output, can be used for cascading
SER
14
Input
QA
15
Output
VCC
16
—
Positive supply
—
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
or supply.
Thermal Pad(1)
Serial input
QA output
1. BQB package only.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
3
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VCC
Supply voltage
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
±20
IOK
Output clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature(3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–0.5
7
UNIT
–65
V
mA
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±4000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
NOM
MAX
2
5
6
V
Supply voltage
UNIT
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
SN74HCS595
THERMAL
4
METRIC(1)
PW (TSSOP)
D (SOIC)
BQB (WQFN)
DYY (SOT-23)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
141.2
122.2
108.4
186.2
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
78.8
80.9
77.3
109.1
°C/W
RθJB
Junction-to-board thermal
resistance
85.8
80.6
74.4
111.0
°C/W
ΨJT
Junction-to-top characterization
parameter
27.7
40.4
12.6
18.0
°C/W
ΨJB
Junction-to-board characterization
parameter
85.5
80.3
74.5
110.9
°C/W
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
SN74HCS595
THERMAL METRIC(1)
RθJC(bot)
(1)
PW (TSSOP)
D (SOIC)
BQB (WQFN)
DYY (SOT-23)
16 PINS
16 PINS
16 PINS
16 PINS
N/A
N/A
54.3
N/A
Junction-to-case (bottom) thermal
resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)(1)
VCC
MIN
VOH
High-level output voltage
VI = VIH or VIL
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
IOH = -20 µA
TYP
0.6
2 V to 6 V
VCC – 0.1
V
V
V
1.6
VCC – 0.002
V
IOH = -6 mA
4.5 V
4.0
4.3
IOH = -7.8 mA
6V
5.4
5.75
IOL = 20 µA
2 V to 6 V
0.002
0.1
IOL = 6 mA
4.5 V
0.18
0.30
VOL
Low-level output voltage
VI = VIH or VIL
6V
0.22
0.33
II
Input leakage current
VI = VCC or 0
6V
±0.1
±1
µA
IOZ
Off-state (high-impedance
state) output current
VO = VCC or 0
6V
±0.5
±5
µA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
(1)
Guaranteed by design.
IOL = 7.8 mA
2 V to 6 V
V
6.6 Timing Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
SRCLK or RCLK
high or low
tw
Pulse duration
SRCLR low
–40°C to 125°C
MAX
MIN
2V
7
9
4.5 V
7
7
6V
7
7
2V
8
10
4.5 V
7
7
6V
7
7
UNIT
MAX
ns
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
5
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
SER before
SRCLK↑
SRCLK↑ before
RCLK↑
tsu
Setup time
SRCLR low before
RCLK↑
SRCLR high
(inactive) before
SRCLK↑
th
Hold time
SER after SRCLK↑
–40°C to 125°C
MAX
MIN
2V
8
13
4.5 V
4
5
6V
3
4
2V
11
18
4.5 V
5
7
6V
4
6
2V
8
13
4.5 V
4
6
6V
4
5
2V
8
13
4.5 V
4
6
6V
4
5
2V
0
0
4.5 V
0
0
6V
0
0
UNIT
MAX
ns
ns
6.7 Switching Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
2V
fmax
Max switching frequency
tpd
Propagation delay
RCLK
tPHL
ten
tdis
QH'
Propagation delay
Enable time
Disable time
SRCLR
OE
OE
QA - QH
QH'
QA - QH
QA - QH
Transition-time
35
19
60
6V
130
TYP
UNIT
MAX
MHz
75
14
19
28
4.5 V
6
8
10
6V
5
7
9
2V
16
21
37
4.5 V
6
9
12
6V
6
8
10
2V
13
19
27
6
8
11
4.5 V
6V
6
8
10
2V
12
18
27
4.5 V
6
9
13
6V
5
8
11
2V
13
16
20
4.5 V
9
11
13
6V
8
10
12
9
16
5
9
4
8
Any output 4.5 V
6V
6
MIN
110
2V
tt
MAX
4.5 V
2V
SRCLK
–40°C to 125°C
TYP
Submit Document Feedback
ns
ns
ns
ns
ns
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
Cpd
VCC
2 V to 6 V
MIN
TYP
40
MAX UNIT
pF
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH’
NOTE:
implies that the output is in 3-State mode.
Figure 6-1. Timing Diagram
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
7
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
6.9 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
Figure 6-2. Output driver resistance in LOW state.
0
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 6-4. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
8
5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 6-3. Output driver resistance in HIGH state.
0.2
0.18
2.5
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 6-5. Supply current across input voltage,
4.5-, 5-, and 6-V supply
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
Test
Point
Test
Point
S1
RL
From Output
Under Test
From Output
Under Test
CL(1)
CL(1)
S2
(1) CL includes probe and test-fixture capacitance.
(1) CL includes probe and test-fixture capacitance.
Figure 7-2. Load Circuit for Push-Pull Outputs
Figure 7-1. Load Circuit for 3-State Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
th
tsu
Figure 7-3. Voltage Waveforms, Pulse Duration
VCC
Data
Input
50%
50%
0V
Figure 7-4. Voltage Waveforms, Setup and Hold
Times
VCC
Input
50%
VCC
Output
Control
50%
50%
50%
0V
tPLH
(1)
tPHL
0V
(1)
tPZL
VOH
Output
50%
VOL
50%
10%
VOL
tPZH(3)
VOH
Output
50%
tPLH(1)
tPHL(1)
Output
Waveform 2
S1 at GND(2)
50%
VOL
tPLZ
(4)
§ 9CC
Output
Waveform 1
S1 at VLOAD(1)
50%
(3)
tPHZ(4)
90%
VOH
50%
§0V
Figure 7-6. Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-5. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-7. Voltage Waveforms, Input and Output Transition Times
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
9
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
8 Detailed Description
8.1 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH¶
Figure 8-1. Logic Diagram (Positive Logic) for the SN74HCS595
8.2 Feature Description
8.2.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving
high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar
currents. The drive capability of this device may create fast edges into light loads so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.2.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.2.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.2.4 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
VCC
Device
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3 Device Functional Modes
Function Table lists the functional modes of the SN74HCS595.
Table 8-1. Function Table
INPUTS
SER
SRCLK
FUNCTION
SRCLR
RCLK
OE
H
Outputs QA – QH are disabled
X
X
X
X
X
X
X
X
L
Outputs QA – QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low. Other stages store the data
of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high. Other stages store the data
of previous stage, respectively.
X
X
H
↑
X
Shift-register data is stored in the storage register.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
11
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
Table 8-1. Function Table (continued)
INPUTS
SER
X
12
SRCLK
↑
SRCLR
RCLK
OE
H
↑
X
FUNCTION
Data in shift register is stored in the storage register, the data is then
shifted through.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HCS595 is used to control seven-segment displays. Utilizing the serial output and
combining a few of the input signals, this implementation reduces the number of I/O pins required to control the
displays from sixteen to four. Unlike other I/O expanders, the SN74HCS595 does not need a communication
interface for control. It can be easily operated with simple GPIO pins.
The OE pin is used to easily disable the outputs when the displays need to be turned off or connected to a
PWM signal to control brightness. However, this pin can be tied low and the outputs of the SN74HCS595 can be
controlled accordingly to turn off all the outputs reducing the I/O needed to three. There is no practical limitation
to how many SN74HCS595 devices can be cascaded. To add more, the serial output will need to be connected
to the following serial input and the clocks will need to be connected accordingly. With separate control for the
shift registers and output registers, the desired digit can be displayed while the data for the next digit is loaded
into the shift register.
At power-up, the initial state of the shift registers and output registers are unknown. To give them a defined state,
the shift register needs to be cleared and then clocked into the output register. An RC can be connected to the
SRCLR pin as shown in the Typical application block diagram to initialize the shift register to all zeros. With the
OE pin pulled up with a resistor, this process can be performed while the outputs are in a high impedance state
eliminating any erroneous data causing issues with the displays.
9.2 Typical Application
VCC
VCC
g
QB
f
QC
a
SER
QD
b
SRCLK
QE
DP
SRCLR
C1
MCU
Seven Segment
QA
R1
RCLK
OE
GND
a
f
QF
c
QG
d
QH
e
b
g
e
c
d
DP
QH¶
VCC
VCC
Seven Segment
QA
g
QB
f
QC
a
SER
QD
b
SRCLK
QE
DP
R2
SRCLR
C2
RCLK
OE
GND
a
f
QF
c
QG
d
QH
e
b
g
e
c
d
DP
QH¶
Figure 9-1. Typical application block diagram
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
13
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS595 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS595 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS595 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed
50 pF.
The SN74HCS595 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HCS595, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS595 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS595 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
SER
QA
QB
QC
QC
QD
QE
QF
Output Registers
QB
Serial Registers
Output Registers
QA
Serial Registers
SER
QD
QE
QF
QG
QG
QH
QH
QH¶
QH¶
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
Figure 9-2. Simplified functional diagram showing clock operation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
15
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused inputs tie to GND or VCC
Avoid 90°
corners for
signal lines
GND VCC
0.1 F
Bypass capacitor
placed close to
the device
QB
1
16
VCC
QC
2
15
QA
QD
3
14
SER
QE
4
13
OE
QF
5
12
RCLK
QG
6
11
SRCLK
QH
7
10
GND
8
9
SRCLR
QH¶
Unused output
left floating
Figure 11-1. Example layout for the SN74HCS595.
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report (SCLA007)
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
17
SN74HCS595
www.ti.com
SCLS803B – OCTOBER 2020 – REVISED MAY 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HCS595
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HCS595BQBR
ACTIVE
WQFN
BQB
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS595
SN74HCS595DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HCS595
SN74HCS595DYYR
ACTIVE
SOT-23-THIN
DYY
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS595
SN74HCS595PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HCS595
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
