SN54HCT244, SN74HCT244
SCLS175G – MARCH 2003 – REVISED DECEMBER 2022
SNx4HCT244 Octal Buffers and Line Drivers With 3-State Outputs
1 Features
3 Description
•
•
•
•
•
•
•
•
These octal buffers and line drivers are designed
specifically to improve both the performance
and density of 3-state memory address drivers,
clockdrivers, and bus-oriented receivers and
transmitters. The SNx4HCT244 devices are organized
as two 4-bit buffers or drivers with separate outputenable (OE) inputs. When OE is low, the device
passes noninverted data from the A inputs to the Y
outputs. When OE is high, the outputs are in the highimpedance state.
Operating Voltage Range of 4.5 V to 5.5 V
High-Current Outputs Drive up to 15 LSTTL Loads
Low Power Consumption: 80-µA Maximum ICC
Typical tpd = 13 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines and Buffer
Memory Address Registers
2 Applications
•
•
•
•
•
•
Device Information
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
PART NUMBER
SN74HCT244
SN54HCT244
(1)
1OE
1A1
1A2
1A3
1A4
1
18
4
16
6
14
8
12
BODY SIZE (NOM)
DB (SSOP, 20)
7.20 mm × 5.30 mm
DW (SOIC, 20)
12.80 mm × 7.50 mm
N (PDIP, 20)
24.33 mm × 6.35 mm
NS (SO, 20)
12.60 mm × 5.30 mm
PW (TSSOP, 20)
6.50 mm × 4.40 mm
DGS (VSSOP, 20)
5.10 mm × 3.00 mm
J (CDIP, 20)
24.20 mm × 6.92 mm
FK (LCCC, 20)
8.89 mm × 8.89 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2OE
2
PACKAGE(1)
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT244, SN74HCT244
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SCLS175G – MARCH 2003 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics: CL = 50 pF........................ 6
6.7 Switching Characteristics: CL = 150 pF...................... 6
6.8 Operating Characteristics........................................... 7
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Example.......................................................11
12 Device and Documentation Support..........................12
12.1 Documentation Support.......................................... 12
12.2 Related Links.......................................................... 12
12.3 Receiving Notification of Documentation Updates..12
12.4 Support Resources................................................. 12
12.5 Trademarks............................................................. 12
12.6 Electrostatic Discharge Caution..............................12
12.7 Glossary..................................................................12
13 Mechanical, Packaging, and Orderable
Information.................................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2022) to Revision G (December 2022)
Page
• Added DGS (SOT) package information............................................................................................................ 1
• Added DGS (SOT) package information............................................................................................................ 3
• Added DGS (SOT) package thermal information............................................................................................... 5
Changes from Revision E (August 2016) to Revision F (May 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 76.6 is now 109.1, DB was 89.4 is now
122.7, N was 44.8 is now 84.6, NS was 71.8 is now 113.4, PW was 97.4 is now 131.8.................................... 5
Changes from Revision D (August 2013) to Revision E (August 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Changed Thermal Information table................................................................................................................... 5
• Added ESD warning........................................................................................................................................... 9
2
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SCLS175G – MARCH 2003 – REVISED DECEMBER 2022
2Y4
1A1
1OE
VCC
2OE
3
2
1
20
19
5 Pin Configuration and Functions
2
19
2OE
2Y4
3
18
1Y1
1A2
4
17
2A4
1A2
4
18
1Y1
2Y3
5
16
1Y2
2Y3
5
17
2A4
1A3
6
15
2A3
1A3
6
16
1Y2
2Y2
7
14
1Y3
2Y2
7
15
2A3
1A4
8
13
2A2
1A4
8
14
1Y3
2Y1
9
12
1Y4
GND
10
11
2A1
J, W, DB, DW, N, NS, PW or DGS Packages 20Pin CDIP, CFP, SSOP, SOIC, PDIP, SO, TSSOP or
VSSOP Top View
2A2
1Y4
2A1
GND
2Y1
Not to scale
13
1A1
12
VCC
11
20
10
1
9
1OE
Not to scale
FK Package 20-Pin LCCC Top View
Pin Functions
PIN
NO.
NAME
1
1 OE
2
3
4
5
I/O(1)
DESCRIPTION
I
Output enable
1A1
I
Input
2Y4
O
Output
1A2
I
Input
2Y3
O
Output
6
1A3
I
Input
7
2Y2
O
Output
8
1A4
I
Input
9
2Y1
O
Output
10
GND
—
Ground
11
2A1
I
Input
12
1Y4
O
Output
13
2A2
I
Input
14
1Y3
O
Output
15
2A3
I
Input
16
1Y2
O
Output
17
2A4
I
Input
18
1Y1
O
Output
19
2 OE
I
Output enable
20
VCC
—
(1)
Power pin
Signal Types: I = Input, O = Output, I/O = Input or Output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
current(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
150
°C
Continuous channel current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
SN74HCT244 in DB, DW, N, NS, or PW package
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification
±2000
JESD22-C101(2)
V
±1000
SN54HCT244 in J, W, or FK package
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
NOM
MAX
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
∆t/∆v
Input transition rise and fall time
500
ns
TA
Operating free-air temperature
(1)
4
MIN
2
V
V
SN54HCT244
–55
125
SN74HCT244
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
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6.4 Thermal Information
SN74HCT244
DB (SSOP)
N (PDIP)
NS (SO)
PW
(TSSOP)
DGS
(VSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
109.1
122.7
84.6
113.4
131.8
130.6
°C/W
76
81.6
72.5
78.6
72.2
68.7
°C/W
DW (SOIC)
THERMAL METRIC
RθJA
Junction-to-ambient thermal
(1)
resistance
RθJC (top)
Junction-to-case (top)
thermal resistance
RθJB
Junction-to-board thermal
resistance
77.6
77.5
65.3
78.4
82.8
85.4
°C/W
ΨJT
Junction-to-top
characterization parameter
51.5
46.1
55.3
47.1
21.5
10.5
°C/W
ΨJB
Junction-to-board
characterization parameter
77.1
77.1
65.2
78.1
82.4
85.0
°C/W
RθJC (bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
MIN
TYP
TA = 25°C
VCC
4.4
4.499
SN54HCT244
4.4
SN74HCT244
VI = VIH or VIL
TA = 25°C
IOH = –6 mA
4.5 V
IOL = 20 µA
VOL
SN74HCT244
3.84
0.001
4.5 V
0.1
0.17
SN54HCT244
SN54HCT244
IOZ
5.5 V
±1000
±0.01
5.5 V
VI = VCC or 0,
IO = 0
∆ICC (1)
One input at 0.5 V
or 2.4 V,
Other inputs at 0 or
VCC
8
5.5 V
160
SN74HCT244
µA
80
TA = 25°C
SN54HCT244
µA
±5
TA = 25°C
SN54HCT244
nA
±0.5
±10
SN74HCT244
ICC
±100
±1000
TA = 25°C
SN54HCT244
V
0.33
±0.1
SN74HCT244
VO = VCC or 0,
VI = VIH or VIL
0.26
0.4
SN74HCT244
VI = VCC or 0
0.1
0.1
TA = 25°C
II
UNIT
V
4.3
SN54HCT244
TA = 25°C
IOL = 6 mA
3.98
3.7
SN74HCT244
VI = VIH or VIL
4.4
SN54HCT244
TA = 25°C
MAX
1.4
5.5 V
SN74HCT244
2.4
3
mA
2.9
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over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
Ci
MIN
TYP
MAX
3
10
4.5 V to
5.5 V
SN54HCT244
10
SN74HCT244
(1)
UNIT
pF
10
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.6 Switching Characteristics: CL = 50 pF
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 7-1 )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TEST
CONDITIONS
MIN
TA = 25°C
4.5 V
tpd
A
Y
MAX
15
28
SN54HCT244
42
SN74HCT244
35
TA = 25°C
5.5 V
TYP
13
25
SN54HCT244
32
TA = 25°C
ten
OE
21
SN54HCT244
53
44
TA = 25°C
5.5 V
19
OE
48
SN74HCT244
40
19
53
44
TA = 25°C
5.5 V
18
32
SN54HCT244
48
SN74HCT244
40
TA = 25°C
4.5 V
8
18
15
TA = 25°C
5.5 V
ns
12
SN54HCT244
SN74HCT244
Y
ns
35
SN54HCT244
SN74HCT244
Y
tt
32
SN54HCT244
TA = 25°C
4.5 V
tdis
35
SN74HCT244
Y
ns
38
SN74HCT244
4.5 V
UNIT
7
11
SN54HCT244
16
SN74HCT244
14
ns
6.7 Switching Characteristics: CL = 150 pF
over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TEST
CONDITIONS
TA = 25°C
4.5 V
tpd
A
Y
6
TYP
MAX
21
45
SN54HCT244
68
SN74HCT244
56
TA = 25°C
5.5 V
MIN
18
40
SN54HCT244
61
SN74HCT244
51
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UNIT
ns
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over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC
MIN
TYP
MAX
25
52
TA = 25°C
4.5 V
ten
OE
Y
SN54HCT244
79
SN74HCT244
65
TA = 25°C
22
SN54HCT244
5.5 V
59
TA = 25°C
tt
Y
17
42
SN54HCT244
63
SN74HCT244
53
TA = 25°C
5.5 V
ns
71
SN74HCT244
4.5 V
47
UNIT
14
38
SN54HCT244
57
SN74HCT244
48
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per buffer or driver
No load
TYP
40
UNIT
pF
6.9 Typical Characteristics
25
25
ten (ns)
24
24
23
23
22
4.5
4.7
4.9
5.1
5.3
VCC (V)
5.5
C002
Figure 6-1. Enable Time vs VCC
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7 Parameter Measurement Information
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
1 kΩ
tPZL
tPHZ
tdis
S2
RL
1 kΩ
tPLZ
––
tpd or tt
LOAD CIRCUIT
2.7 V
Input 1.3 V
0.3 V
2.7 V
CL
S1
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50 pF
50 pF
or
150 pF
3V
1.3 V
0.3 V 0 V
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
tf
1.3 V
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
Output
Control
(Low-Level
Enabling)
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
≈VCC
Output
Waveform 1
(See Note B)
1.3 V
10%
tPZH
VOL
tPHZ
Output
Waveform 2
(See Note B)
1.3 V
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SNx4HCT244 device is organized as two 4-bit buffers and line drivers with separate output-enable ( OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must
be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking
capability of the driver.
8.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74HCT244 device can drive up to 15 LSTTL loads. This device has low power consumption of 80-µA ICC.
The SN74HCT244 also has 3 state outputs that allow the outputs to go to high impedance, low or high.
8.4 Device Functional Modes
Table 8-1 lists the functions of the SNx4HC244.
Table 8-1. Function Table
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74HC244 is a high-drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern.
9.2 Typical Application
Regulated 5V
SN74HCT244
1OE
MCU or
System
Logic
x
x
x
A1
x
x
x
A4
VCC
Y1
x
x
x
Y4
x
x
x
MCU
System
Logic
LEDS
GND
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Figure 9-1. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive creates fast edges into light loads, so consider routing and
load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
• For rise time and fall time specifications, see Δt/ΔV in Recommended Operating Conditions.
• For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommend output conditions:
• Load currents must not exceed the IO maximum per output and must not exceed the continuous current
through VCC or GND total current for the part. These limits are located in Absolute Maximum Ratings.
• Outputs must not be pulled above VCC.
10
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9.2.3 Application Curve
22
tpd (ns)
21
20
19
18
17
4.5
4.7
4.9
5.1
5.3
VCC (V)
5.5
C001
Figure 9-2. Propagation Delay vs VCC
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC terminals, then TI recommends 0.01-µF
or 0.022-µF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The
bypass capacitor must be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or
when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states.
Specified in Figure 11-1 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagram
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Product Folder Links: SN54HCT244 SN74HCT244
11
SN54HCT244, SN74HCT244
www.ti.com
SCLS175G – MARCH 2003 – REVISED DECEMBER 2022
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HCT244
Click here
Click here
Click here
Click here
Click here
SN74HCT244
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT244 SN74HCT244
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8513001VRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8513001VR
A
SNV54HCT244J
5962-8513001VSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8513001VS
A
SNV54HCT244W
85130012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85130012A
SNJ54HCT
244FK
8513001RA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8513001RA
SNJ54HCT244J
Samples
JM38510/65755B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65755B2A
Samples
JM38510/65755BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65755BRA
Samples
M38510/65755B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65755B2A
Samples
M38510/65755BRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65755BRA
Samples
SN54HCT244J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HCT244J
Samples
SN74HCT244DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244DWE4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244DWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244DWRE4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244DWRG4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244N
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT244N
Samples
Addendum-Page 1
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74HCT244NE4
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT244N
Samples
SN74HCT244NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT244
Samples
SN74HCT244PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244PWE4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244PWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SN74HCT244PWT
ACTIVE
TSSOP
PW
20
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT244
Samples
SNJ54HCT244FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85130012A
SNJ54HCT
244FK
SNJ54HCT244J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8513001RA
SNJ54HCT244J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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