SN74HCT652DWG4

SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 D D D D D D D Operating Voltage Range of 4.5 V to 5.5 V Low Power Consumption, 80-µA Max ICC Typical tpd = 12 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads SN54HCT652 . . . FK PACKAGE (TOP VIEW) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 NC A4 A5 A6 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 OEBA B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND OEAB SAB CLKAB NC VCC CLKBA SAB SN54HCT652 . . . JT OR W PACKAGE SN74HCT652 . . . DW OR NT PACKAGE (TOP VIEW) NC – No internal connection description/ordering information The ’HCT652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. A low input level selects real-time data; a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices. ORDERING INFORMATION PDIP – NT –40°C to 85°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube SN74HCT652NT Tube SN74HCT652DW Tape and reel SN74HCT652DWR CDIP – JT Tube SNJ54HCT652JT SNJ54HCT652JT CFP – W Tube SNJ54HCT652W SNJ54HCT652W LCCC – FK Tube SNJ54HCT652FK SNJ54HCT652FK SOIC – DW SN74HCT652NT HCT652 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 description/ordering information (continued) Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. FUNCTION TABLE DATA I/O† INPUTS OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1– A8 B1– B8 L H H or L H or L X X Input Input Isolation L H ↑ ↑ X X Input H ↑ H or L X Input H H ↑ ↑ X X‡ Input Unspecified‡ Store A and B data X X Input Output Store A in both registers L X H or L ↑ X Unspecified‡ Input Hold A, store B L L ↑ ↑ X X X‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus H L H or L H or L H H Output Store A, hold B † The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs. ‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered to load both registers. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCLS179D – MARCH 1984 – REVISED MARCH 2003 22 SBA L 3 21 OEAB OEBA H H 21 OEBA H X H 1 23 2 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X 2 SAB L 22 SBA X BUS B BUS A BUS A 3 OEAB X L L 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 3 21 1 23 2 22 SBA OEAB H OEBA L CLKAB CLKBA SAB SBA H or L H or L H H X X X STORAGE FROM A, B, OR A AND B TRANSFER STORED DATA TO A AND/OR B Pin numbers shown are for the DW, JT, NT, and W packages. Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W (see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-3. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 recommended operating conditions (see Note 4) SN54HCT652 NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO tt Output voltage 0 High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT652 MIN 2 2 Input transition (rise and fall) time V V 0.8 VCC VCC UNIT 0 0 500 0.8 V VCC VCC V 500 ns V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –6 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 45V 4.5 II Control inputs IOZ A or B ICC ∆ICC† Ci MIN TA = 25°C TYP MAX SN54HCT652 MIN MAX SN74HCT652 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 V VI = VCC or 0 VO = VCC or 0, VI = VIH or VIL, Data = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA 5.5 V ±0.01 ±0.5 ±10 ±5 µA VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC 5.5 V 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V 4.5 V to 5.5 V Control inputs † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) fclock l k Clock frequency tw Pulse duration, duration CLKBA or CLKAB high or low tsu S t time, Setup ti A before b f CLKAB↑ or B b before f CLKBA↑ th time A after CLKAB↑ or B after CLKBA↑ Hold time, VCC TA = 25°C MIN MAX SN54HCT652 4.5 V 25 17 20 5.5 V 28 19 22 MIN MAX SN74HCT652 MIN 4.5 V 20 30 25 5.5 V 18 27 23 4.5 V 15 23 19 5.5 V 14 21 17 4.5 V 5 5 5 5.5 V 5 5 5 MAX UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLKBA or CLKAB tpd d A or B A or B B or A SBA or SAB† A or B ten OEBA or OEAB A or B tdis di OEBA or OEAB A or B tt Any VCC MIN TA = 25°C TYP MAX SN54HCT652 MIN MAX SN74HCT652 MIN 4.5 V 25 35 17 20 5.5 V 28 40 19 22 MAX UNIT MHz 4.5 V 18 36 54 45 5.5 V 16 32 49 41 4.5 V 14 27 41 34 5.5 V 12 24 37 31 4.5 V 20 38 57 48 5.5 V 17 34 51 43 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 25 49 74 61 5.5 V 22 44 67 55 4.5 V 9 12 18 15 5.5 V 7 11 16 14 ns ns ns ns † These parameters are measured with the internal output state of the storage register opposite that of the bus input. switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd d ten FROM (INPUT) TO (OUTPUT) CLKBA or CLKAB A or B A or B B or A SBA or SAB† A or B A or B OEBA or OEAB tt Any VCC TA = 25°C MIN TYP MAX SN54HCT652 MIN MAX SN74HCT652 MIN MAX 4.5 V 24 53 80 66 5.5 V 22 47 72 60 4.5 V 22 44 70 55 5.5 V 20 39 60 50 4.5 V 26 55 83 69 5.5 V 24 49 74 62 4.5 V 33 66 100 82 5.5 V 30 59 90 74 4.5 V 17 42 63 53 5.5 V 14 38 57 48 UNIT ns ns ns † These parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF SN54HCT652, SN74HCT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS179D – MARCH 1984 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER ten RL tdis CL (see Note A) S2 tPZH RL 1 kΩ tPZL tPHZ 1 kΩ CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ tpd or tt 50 pF or 150 pF –– LOAD CIRCUIT 3V High-Level Pulse 1.3 V 3V Reference Input 1.3 V 0V 1.3 V tsu 0V tw Data Input 1.3 V 0.3 V 3V Low-Level Pulse 1.3 V 1.3 V Output Control (Low-Level Enabling) 3V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH 1.3 V 10% V OL tf 1.3 V 10% tf 3V 1.3 V 0.3 V 0 V tf 3V 1.3 V 1.3 V 0V tPZL Output Waveform 1 (See Note B) tPLZ ≈VCC 1.3 V 10% tPZH tPLH 1.3 V 10% 2.7 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 2.7 V tr 0V Input th 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES Output Waveform 2 (See Note B) VOL tPHZ 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74HCT652DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT652 SN74HCT652DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT652 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of