SN54HCT74, SN74HCT74
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
SNx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flips With Clear and Preset
1 Features
2 Description
•
•
•
•
•
•
•
The ’HCT74 devices contain two independent D-type
positive-edge-triggered flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets the
outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the
data (D) input meeting the setup time requirements
are transferred to the outputs on the positive-going
edge of the clock (CLK) pulse. Clock triggering occurs
at a voltage level and is not directly related to the
rise time of CLK. Following the hold-time interval, data
at the D input may be changed without affecting the
levels at the outputs.
Operating voltage range of 4.5 V to 5.5 V
Outputs can drive up to 10 LSTTL loads
Low power consumption, 40-μA max ICC
Typical tpd = 17 ns
±4-mA output drive at 5 V
Low input current of 1 μA max
Inputs are TTL-voltage compatible
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HCT74D
SOIC (14)
8.65 mm × 3.90 mm
SN74HCT74DB
SSOP (14)
6.20 mm × 5.30 mm
SN74HCT74N
PDIP (14)
19.31 mm × 6.35 mm
SN74HCT74NS
SO (14)
10.20 mm × 5.30 mm
SN74HCT74PW
TSSOP (14)
5.00 mm × 4.40 mm
SNJ54HCT74FK
LCCC (20)
8.89 mm × 8.45 mm
SNJ54HCT74W
CFP (14)
9.21 mm × 6.29 mm
SNJ54HCT74J
CDIP (14)
19.55 mm × 6.71 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings ....................................... 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements.................................................. 5
5.6 Switching Characteristics ...........................................6
5.7 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Receiving Notification of Documentation Updates..10
10.2 Support Resources................................................. 10
10.3 Trademarks............................................................. 10
10.4 Electrostatic Discharge Caution..............................10
10.5 Glossary..................................................................10
11 Mechanical, Packaging, and Orderable
Information.................................................................... 10
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2022) to Revision G (October 2022)
Page
• Increased RθJA for packages: D (86 to 138.7); N (80 to 103.8); NS (76 to 129.3); PW (113 to 157.6)............. 4
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
J, W, D, DB, N, NS, or PW package
14-Pin CDIP, CFP, SOIC, SSOP, PDIP, SO, or TSSOP
Top View
NC - No internal connection
FK Package
20-Pin LCCC
Top View
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
3
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
± 20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
± 20
mA
IO
Continuous output current
VO = 0 to VCC
± 25
mA
± 50
mA
150
℃
150
℃
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HCT74(2)
SN74HCT74
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
Vcc = 4.5 V to 5.5 V
VIL
Low-level input voltage
Vcc = 4.5 V to 5.5 V
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
Δt/Δv
Input transition rise/fall time
500
ns
TA
Operating free-air temperature
85
°C
(1)
(2)
2
V
2
V
0.8
500
−55
125
−40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HCT74 is in product preview.
5.3 Thermal Information
THERMAL METRIC
DB (SSOP)
N (PDIP)
NS (SO)
PW (TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal
(1)
resistance
138.7
109.8
61.1
88.4
114.7
°C/W
RθJC (top)
Junction-to-case (top) thermal
resistance
93.8
54.7
48.9
46
44.3
°C/W
RθJB
Junction-to-board thermal
resistance
94.7
58.6
40.9
48.9
57.6
°C/W
ΨJT
Junction-to-top characterization
parameter
49.1
15.5
28.5
13.8
4.8
°C/W
ΨJB
Junction-to-board
characterization parameter
94.3
58
40.6
48.4
57
°C/W
RθJC (bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VI = VIH or VIL
VOL
VI = VIH or VIL
II
VI = VCC or 0
ICC
Vi = VCC or 0,
ΔICC (1)
IOH = −20 μA
IOL = 20 μA
4.5 V
IOL = 4 mA
5.5 V
IO = 0
MAX
MIN
SN74HCT74
MIN
TYP
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
MIN
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±0.1
±100
±1000
±1000
nA
4
80
40
μA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
Ci
(1)
(2)
4.5 V
IOH = −4 mA
SN54HCT74(2)
TA = 25°C
VCC
5.5 V
4.5 V to 5.5 V
V
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
SN54HCT74 is in product preview.
5.5 Timing Requirements
overrecommended operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
PRE or CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
PRE or CLR inactive
th
Hold time, data after CLK↑
(1)
SN54HCT74 is in product preview.
SN54HCT74(1)
TA = 25°C
MIN
MAX
MIN
MAX
SN74HCT74
MIN
MAX
4.5 V
27
18
22
5.5 V
30
20
24
4.5 V
16
24
20
5.5 V
14
21
18
4.5 V
18
27
23
5.5 V
16
24
21
4.5 V
12
18
15
5.5 V
11
16
14
4.5 V
0
0
0
5.5 V
0
0
0
4.5 V
0
0
0
5.5 V
0
0
0
UNIT
MHz
ns
ns
ns
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
5
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
fmax
PRE or CLR
Q or Q
CLK
Q or Q
tpd
tt
(1)
Q or Q
SN54HCT74(1)
TA = 25°C
MAX
MIN
MAX
SN74HCT74
MIN
TYP
MIN
4.5 V
27
40
18
22
5.5 V
30
46
20
24
MAX
UNIT
MHz
4.5 V
21
35
53
44
5.5 V
17
31
48
40
4.5 V
20
28
42
35
5.5 V
18
25
38
31
4.5 V
8
15
22
19
5.5 V
7
14
20
17
ns
ns
SN54HCT74 is in product preview.
5.7 Operating Characteristics
TA = 25℃
Cpd
6
PARAMETER
TEST CONDITIONS
Power dissipation capacitance per flip-flop
No load
Submit Document Feedback
TYP
35
UNIT
pF
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 6-2. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 6-3. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH
(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
7
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed
without affecting the levels at the outputs.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS
(1)
8
OUTPUT
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H(1)
H(1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
9
SN54HCT74, SN74HCT74
www.ti.com
SCLS169G – DECEMBER 1982 – REVISED OCTOBER 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54HCT74 SN74HCT74
PACKAGE OPTION ADDENDUM
www.ti.com
21-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
JM38510/65352B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352B2A
Samples
JM38510/65352BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352BCA
Samples
JM38510/65352BDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352BDA
Samples
M38510/65352B2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352B2A
Samples
M38510/65352BCA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352BCA
Samples
M38510/65352BDA
ACTIVE
CFP
W
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65352BDA
Samples
SN74HCT74D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
Samples
SN74HCT74DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
Samples
SN74HCT74DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HCT74
Samples
SN74HCT74DRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
Samples
SN74HCT74DT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
Samples
SN74HCT74N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT74N
Samples
SN74HCT74NE4
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT74N
Samples
SN74HCT74NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
Samples
SN74HCT74PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
Samples
SN74HCT74PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HT74
Samples
SN74HCT74PWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Oct-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
