SN74LS148D








  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 D D ’147, ’LS147 Encode 10-Line Decimal to 4-Line BCD Applications Include: − Keyboard Encoding − Range Selection D D SN54147, SN54LS147 . . . J OR W PACKAGE SN74147, SN74LS147 . . . D OR N PACKAGE (TOP VIEW) 4 5 6 7 8 C B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 ’148, ’LS148 Encode 8 Data Lines to 3-Line Binary (Octal) Applications Include: − n-Bit Encoding − Code Converters and Generators SN54148, SN54LS148 . . . J OR W PACKAGE SN74148, SN74LS148 . . . D, N, OR NS PACKAGE (TOP VIEW) VCC NC D 3 2 1 9 A 4 5 6 7 EI A2 A1 GND 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC E0 GS 3 2 1 0 A0 5 4 NC VCC E0 D 3 NC 2 1 6 7 NC EI A2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 GS 3 NC 2 1 A1 GND NC A0 0 4 B GND NC A 9 6 7 NC 8 C 16 2 SN54LS148 . . . FK PACKAGE (TOP VIEW) 5 4 NC VCC NC SN54LS147 . . . FK PACKAGE (TOP VIEW) 1 NC − No internal connection TYPE TYPICAL DATA DELAY TYPICAL POWER DISSIPATION ’147 10 ns 225 mW ’148 10 ns 190 mW ’LS147 15 ns 60 mW ’LS148 15 ns 60 mW NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated   !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%-  )!,'&$% &")+#$ $  3 #++ )#!#"($(!% #!( $(%$(, '+(%% $.(!0%( $(,-  #++ $.(! )!,'&$% )!,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 description/ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA PDIP − N 0°C to 70°C Tube SN74LS148N Tube SN74LS148D Tape and reel SN74LS148DR SOP − NS Tape and reel SN74LS148NSR 74LS148 CDIP − J Tube SNJ54LS148J SNJ54LS148J CFP − W Tube SNJ54LS148W SNJ54LS148W SOIC − D −55°C −55 C to 125 125°C C TOP-SIDE MARKING SN74LS148N LS148 LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE − ’147, ’LS147 INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 D C B A H H H H H H H H H H H H H X X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L X L H H H H H H H H H L H L H H H H H H H H H H H L H = high logic level, L = low logic level, X = irrelevant 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 FUNCTION TABLE − ’148, ’LS148 OUTPUTS INPUTS EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H H = high logic level, L = low logic level, X = irrelevant POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 ’147, ’LS147 logic diagram (positive logic) (11) 1 2 3 4 (12) (9) (13) (1) (7) 5 6 7 8 9 B (2) (3) (4) (6) C (5) (14) (10) Pin numbers shown are for D, J, N, and W packages. 4 A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 ’148, ’LS148 logic diagram (positive logic) 0 (10) (15) 1 2 (14) (11) 4 6 7 EI A0 (13) (1) (7) 5 G5 (12) (9) 3 EO A1 (2) (3) (4) (6) A2 (5) Pin numbers shown are for D, J, N, NS, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 schematics of inputs and outputs ’147, ’148 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC
 Ω NOM Req Input Output 0 input (’148): Req = 2 kΩ NOM All other inputs: Req = 4 kΩ NOM ’LS147, ’LS148 EQUIVALENT OF ALL INPUTS TYPICAL OF ALL OUTPUTS VCC VCC 120 Ω NOM Req Input Output ’LS148 inputs 1–7: Req = 9 kΩ NOM All other inputs: Req = 18 kΩ NOM 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’147, ’148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS147, ’LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the eight data lines, 0 through 7. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54’ VCC IOH Supply voltage IOL TA Low-level output current MIN NOM 4.5 5 High-level output current Operating free-air temperature SN74’ MAX MIN NOM 5.5 4.75 5 −800 125 MAX MIN NOM 5.25 4.5 5 −800 16 −55 SN54LS’ 70 MAX MIN NOM 5.5 4.75 5 −400 16 0 SN74LS’ 4 −55 125 0 MAX UNIT 5.25 V −400 µA 8 mA 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS† PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL ’147 MIN TYP‡ MAX ’148 MIN TYP‡ 2 2 Low-level input voltage V 0.8 V −1.5 −1.5 V II = −12 mA VIH = 2 V, IOH = −800 µA Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA II Input current at maximum input voltage VCC = MIN, VI = 5.5 V 1 High-level input current 0 input IIH VCC = MAX, VI = 2.4 V 40 Low-level input current 0 input IIL VCC = MAX, VI = 0.4 V −1.6 3.3 2.4 0.2 3.3 0.4 0.2 V 0.4 1 40 Any input except 0 UNIT 0.8 VCC = MIN, VCC = MIN, VIL = 0.8 V, 2.4 MAX 80 V mA µA A −1.6 IOS Any input except 0 Short-circuit output current§ ICC Supply current VCC = MAX −35 VCC = MAX (See Note 5) −85 −3.2 −35 −85 Condition 1 50 70 40 60 Condition 2 42 62 35 55 mA mA mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 5: For ’147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. SN54147, SN74147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1) 8 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Any tPLH tPHL Any Any WAVEFORM TEST CONDITIONS In-phase output Out-of-phase output POST OFFICE BOX 655303 CL = 15 pF, RL = 400 Ω • DALLAS, TEXAS 75265 MIN TYP MAX 9 14 7 11 13 19 12 19 UNIT ns ns 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 SN54148, SN74148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1) PARAMETER† FROM (INPUT) TO (OUTPUT) tPLH tPHL 1–7 A0, A1, or A2 In-phase output tPLH tPHL 1–7 A0, A1, or A2 Out-of-phase output tPLH tPHL 0–7 EO Out-of-phase output tPLH tPHL 0–7 GS In-phase output tPLH tPHL EI A0, A1, or A2 In-phase output tPLH tPHL EI GS In-phase output tPLH tPHL EI EO In-phase output WAVEFORM TEST CONDITIONS MIN CL = 15 pF, RL = 400 Ω TYP MAX 10 15 9 14 13 19 12 19 6 10 14 25 18 30 14 25 10 15 10 15 8 12 10 15 10 15 17 30 UNIT ns ns ns ns ns ns ns † tPLH = propagation delay time, low-to-high-level output. tPHL = propagation delay time, high-to-low-level output. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage Input current at maximum input voltage ’LS148 inputs 1–7 II High-level input current ’LS148 inputs 1–7 IIH Low-level input current ’LS148 inputs 1–7 IIL TEST CONDITIONS† SN54LS’ MIN TYP‡ MAX 2 2 Low-level input voltage All other inputs All other inputs IOS All other inputs Short-circuit output current§ ICC Supply current VCC = MIN, VCC = MIN, VIL = 0.8 V, II = −18 mA VIH = 2 V, IOH = −400 µA VCC = MIN, VIH = 2 V, VIL = VIL MAX IOL = 4 mA VCC = MAX, VI = 7 V VCC = MAX, VI = 2.7 V VCC = MAX, VI = 0.4 V V 0.7 0.8 V −1.5 V 3.4 0.25 UNIT −1.5 2.7 0.4 3.4 V 0.25 0.4 0.35 0.5 V IOL = 8 mA VCC = MAX VCC = MAX (See Note 6) 2.5 SN74LS’ MIN TYP‡ MAX 0.2 0.2 0.1 0.1 40 40 20 20 −0.8 −0.8 −0.4 −0.4 mA −20 −100 −20 −100 Condition 1 12 20 12 20 Condition 2 10 17 10 17 µA A mA mA mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 6: For ’LS147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For ’LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 SN54LS147, SN74LS147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Any tPLH tPHL Any Any WAVEFORM TEST CONDITIONS MIN In-phase output Out-of-phase output CL = 15 pF, RL = 2 kkΩ TYP MAX 12 18 12 18 21 33 15 23 UNIT ns ns SN54LS148, SN74LS148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2) PARAMETER† FROM (INPUT) TO (OUTPUT) tPLH tPHL 1–7 A0, A1, or A2 In-phase output tPLH tPHL 1–7 A0, A1, or A2 Out-of-phase output tPLH tPHL 0–7 EO Out-of-phase output tPLH tPHL 0–7 GS In-phase output tPLH tPHL EI A0, A1, or A2 In-phase output tPLH tPHL EI GS In-phase output tPLH tPHL EI EO In-phase output WAVEFORM TEST CONDITIONS CL = 15 pF, RL = 2 kΩ k † tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX 14 18 15 25 20 36 16 29 7 18 25 40 35 55 9 21 16 25 12 25 12 17 14 36 12 21 23 35 UNIT ns ns ns ns ns ns ns 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.5 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 1 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu 0V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 1.5 V 3V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.5 V tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 0V Output Control (low-level enabling) 1.5 V tPLH 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.3 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V 5 kΩ Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 1.3 V Output Control (low-level enabling) 0V tPLH In-Phase Output (see Note D) 1.3 V 0V 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 3V 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th Waveform 2 (see Notes C and D) VOL + 0.5 V tPHZ VOH 1.3 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 







  



             
SDLS053B − OCTOBER 1976 − REVISED MAY 2004 APPLICATION INFORMATION 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI ’148/’LS148 ’148/LS148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS ’08/’LS08 0 1 2 Priority Flag (active low) 3 Encoded Data (active low) 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI ’148/’LS148 ’148/’LS148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS ’HC00 0 1 2 Priority Flag (active high) 3 Encoded Data (active high) Figure 3. Priority Encoder for 16 Bits Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be considered when strobing the outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 78027012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK 7802701EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J Samples 7802701FA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W Samples JM38510/36001B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001B2A Samples JM38510/36001BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001BEA Samples JM38510/36001BFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001BFA Samples M38510/36001B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001B2A Samples M38510/36001BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001BEA Samples M38510/36001BFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 36001BFA Samples SN54LS148J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54LS148J Samples SN74LS148D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 Samples SN74LS148DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS148 Samples SN74LS148N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS148N Samples SN74LS148NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS148 Samples SNJ54LS148FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 78027012A SNJ54LS 148FK SNJ54LS148J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7802701EA SNJ54LS148J Addendum-Page 1 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Jun-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54LS148W ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7802701FA SNJ54LS148W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of