SN74LS221NG4




 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 D Dual Versions of Highly Stable SN54121 D TYPE MAXIMUM OUTPUT PULSE LENGTH(S) SN54221 21 SN74221 28 SN54LS221 49 SN74LS221 70 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A SN54LS221 . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 1R ext /Cext D 1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND description/ordering information 1CLR 1Q NC 2Q 2Cext 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2R ext/Cext The ’221 and ’LS221 devices are dual multivibrators with performance characteristics virtually identical to those of the ’121 devices. Each multivibrator features a negative-transitiontriggered input and a positive-transition-triggered input, either of which can be used as an inhibit input. 1Cext 1Q NC 2Q 2CLR GND NC 2A 2B D SN54221, SN54LS221 . . . J PACKAGE SN74221 . . . N PACKAGE SN74LS221 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) and SN74121 One Shots SN54221 and SN74221 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN54121 and SN74121 One Shots Pinout Is Identical to the SN54123, SN74123, SN54LS123, and SN74LS123 Overriding Clear Terminates Output Pulse NC − No internal connection ORDERING INFORMATION PDIP − N 0°C to 70°C −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA Tube TOP-SIDE MARKING SN74221N SN74221N SN74LS221N SN74LS221N Tube SN74LS221D Tape and reel SN74LS221DR SOP − NS Tape and reel SN74LS221NSR 74LS221 SSOP − DB Tape and reel SN74LS221DBR LS221 SNJ54221J SNJ54221J SNJ54LS221J SNJ54LS221J SNJ54LS221FK SNJ54LS221FK SOIC − D CDIP − J Tube LCCC − FK Tube LS221 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated    !"# $ %&'# "$  (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$,  (+&%#$ %!(*"# # 2343 "** (""!'#'$ "' #'$#'+ &*'$$ #-'/$' #'+,  "** #-' (+&%#$ (+&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 description/ordering information (continued) Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics waveforms. Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221, 2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively. Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed. FUNCTION TABLE (each monostable multivibrator) INPUTS OUTPUTS CLR A B Q Q L X X L H X H X L H X X L L H L ↑ † † H † † H † † H ↑‡ ↓ L H † Pulsed-output patterns are tested during AC switching at 25°C with Rext = 2 kΩ, and Cext = 80 pF. ‡ This condition is true only if the output of the latch formed by the two NAND gates has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 timing component connections VCC Rext To Cext Terminal To Rext/Cext Terminal NOTE: Due to the internal circuit, the Rext/Cext terminal never is more positive than the Cext terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 schematics of inputs and outputs SN54/74221 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC 100 Ω NOM Req Input Output A Input: Req = 4 kΩ NOM B, CLR Input: Req = 2 kΩ NOM SN54/74LS221 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC 120 Ω NOM Req Input Output A Input: Req = 25 kΩ NOM B Input: Req = 15.4 kΩ NOM CLR: Req = 12.5 kΩ NOM 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI (see Note 1): ’LS221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V ’221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54221 VCC IOH Supply voltage IOL Low-level output current ∆v/∆t MIN NOM 4.5 5 High-level output current Rise or fall of input pulse rate SN74221 MAX MIN NOM 5.5 4.75 5 −800 16 MAX UNIT 5.25 V −800 µA 16 mA B input 1* 1 V/s A input 1* 1 V/µs TA Operating free-air temperature −55 125 0 70 °C ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† VT+ Positive-going threshold voltage, B input VCC = MIN VT− Negative-going threshold voltage, B input VCC = MIN MIN SN54221 TYP‡ MAX 1.55 VIK VOH VCC = MIN, VCC = MIN, II = −12 mA IOH = −800 µA VOL II VCC = MIN, VCC = MAX, IOL = 16 mA VI = 5.5 V 0.8* 1.35 2.4 3.4 CLR, B input VCC = MAX, VI = 2.4 V 0.2 VCC = MAX, VI = 0.4 V A input IIL CLR, B input IOS§ ICC VCC = MAX Quiescent Triggered 2* SN74221 TYP‡ MAX 1.55 0.8 1.35 2.4 3.4 −1.5 A input IIH MIN −20 VCC = MAX 2 0.2 1 1 40 80 80 −1.6 −1.6 −3.2 −3.2 −18 V V 0.4 40 −55 V V −1.5 0.4 UNIT −55 26 50* 26 50 46 80* 46 80 V mA µA A mA mA mA ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. timing requirements over recommended ranges of supply voltage and operating free-air temperature tw Pulse duration tsu Setup time, inactive-state¶ Rext External timing resistance Cext External timing capacitance Output duty cycle POST OFFICE BOX 655303 SN74221 MIN MAX A or B input 50 50 CLR 20 20 CLR 15 15 MAX ns 1.4* 30* 1.4 40 kΩ 0* 1000* 0 1000 µF 67% 67% Rext = MAX Rext 90% 90% • DALLAS, TEXAS 75265 UNIT ns Rext = 2 kΩ ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ¶ Inactive-state setup time also is referred to as recovery time. 6 SN54221 MIN 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 switching characteristics VCC = 5 V, RL = 400 Ω, TA = 25_C (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) SN54221 TEST CONDITIONS MIN A tPLH B Q Cext = 80 pF, A tPHL tPHL tPLH tw B Rext = 2 kΩ Q TYP MAX TYP MAX 45 70 45 70 35 55 35 55 50 80 50 80 40 65 40 65 Q CLR A or B Q Q or Q SN74221 MIN 27 27 40 40 Cext = 80 pF, Rext = 2 kΩ Cext = 80 pF, Rext = 2 kΩ 70 110 150 70 110 150 Cext = 0, Rext = 2 kΩ 17 30 50 17 30 50 Cext = 100 pF, Rext = 10 kΩ 650 700 750 650 700 750 Cext = 1 µF, Rext = 10 kΩ 6.5* 7 7.5* 6.5 7 7.5 MAX MIN NOM 5.5 4.75 5 UNIT ns ns ns ms ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. recommended operating conditions (see Note 4) SN54LS221 VCC IOH Supply voltage IOL Low-level output current ∆v/∆t MIN NOM 4.5 5 High-level output current −400 4 B input Rise or fall of input pulse rate SN74LS221 A input 1* 1* MAX UNIT 5.25 V −400 µA 8 mA 1 V/s 1 V/µs TA Operating free-air temperature −55 125 0 70 °C ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VT+ Positive-going threshold voltage, B input VCC = MIN VT− Negative-going threshold voltage, B input VCC = MIN VIK VOH MIN 1 VCC = MIN, VCC = MIN, II = −18 mA IOH = −400 µA VOL VCC = MIN IOL = 4 mA IOL = 8 mA II VCC = MAX, VI = 7 V VCC = MAX, VI = 2.7 V IIH SN54LS221 TYP‡ MAX TEST CONDITIONS† 0.7* 0.9 2.5 3.4 CLR, B input IOS§ ICC VCC = MAX, 0.25 Triggered 1 V 2* 0.8 0.9 2.7 3.4 VI = 0.4 V −20 VCC = MAX 2 V −1.5 0.4 0.4 0.35 0.5 mA µA 20 20 −0.4 −0.8 −0.8 −20 V 0.1 −0.4 −100 V V 0.25 0.1 VCC = MAX Quiescent UNIT −1.5 A input IIL SN74LS221 TYP‡ MAX MIN −100 4.7 11 4.7 11 19 27* 19 27 mA mA mA ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. timing requirements over recommended ranges of supply voltage and operating free-air temperature SN54LS221 MIN tw Pulse duration tsu Setup time, inactive state¶ Rext External timing resistance Cext External timing capacitance 50 50 40 40 RT = 2 kΩ RT = MAX Rext POST OFFICE BOX 655303 MIN CLR ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. ¶ Inactive-state setup time also is referred to as recovery time. 8 SN74LS221 A or B CLR Output duty cycle MAX • DALLAS, TEXAS 75265 15 MAX UNIT ns 15 ns 1.4* 70* 1.4 100 kΩ 0* 1000* 0 1000 µF 50% 50% 90% 90% 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 switching characteristics VCC = 5 V, RL = 2 kΩ, TA = 25_C (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) SN54LS221 TEST CONDITIONS MIN A tPLH B Q Cext = 80 pF, A tPHL tPHL tPLH tw B Rext = 2 kΩ Q Q CLR A or B Q Q or Q SN74LS221 TYP MAX 45 MIN TYP MAX 70 45 70 35 55 35 55 50 80 50 80 40 65 40 65 35 55 35 55 44 65 44 65 Cext = 80 pF, Rext = 2 kΩ Cext = 80 pF, Rext = 2 kΩ 70 120 150 70 120 150 Cext = 0, Rext = 2 kΩ 20 47 70 20 47 70 Cext = 100 pF, Rext = 10 kΩ 670 740 810 670 740 810 Cext = 1 µF, Rext = 10 kΩ 6* 6.9 7.5* 6 6.9 7.5 UNIT ns ns ns ms ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION tw 3V B† 0V ≥ 60 ns 3V CLR 0V tPLH tPHL VOH Q VOL tPHL tPLH VOH Q VOL CONDITION 1: TRIGGER FROM B, THEN CLR 3V B† 0V ≥ 60 ns 3V CLR 0V VOH Q VOL CONDITION 2: TRIGGER FROM B, THEN CLR 3V B† 0V ≥ 50 ns ≥0 tsu 3V CLR 0V tw Triggered VOH Q VOL Not Triggered CONDITION 3: CLR OVERRIDING B, THEN TRIGGER FROM B † A is low. Figure 1. Switching Characteristics 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION 3V B† 0V ≥ 50 ns ≥ 50 ns 3V CLR 0V VOH Q VOL CONDITION 4: TRIGGERING FROM POSITIVE TRANSITION OF CLR tw 3V A‡ 0V ≥ 60 ns 3V CLR 0V tPLH tPHL VOH Q VOL tPHL tPLH VOH Q VOL CONDITION 5: TRIGGER FROM A, THEN CLR 3V A‡ 0V tw VOH Q VOL tw VOH Q VOL CONDITION 6: TRIGGER FROM A † A is low. ‡ B and CLR are high. NOTES: A. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50Ω; for SN54/74221, tr ≤ 7 ns, tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns. B. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points for the SN54/74LS221. Figure 1. Switching Characteristics (Continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC Test Point RL From Output Under Test (see Note B) CL = 15 pF (see Note A) High-Level Pulse tw Low-Level Pulse LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS VOLTAGE WAVEFORMS PULSE DURATIONS 3V Input tPLH 3V Timing Input VOH In-Phase Output 0V tsu th tPHL 3V Data Input 0V 0V tPHL VOL tPLH VOH Out-of-Phase Output VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. B. C. D. CL includes probe and jig capacitance. All diodes are 1N3064 or equivalent. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω and, for SN54/74221, tr ≤ 7 ns, tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns. E. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points for the SN54/74LS221. Figure 2. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



 
 
  
 

  
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (SN54/74221 ONLY)† VARIATION IN OUTPUT PULSE vs SUPPLY VOLTAGE DISTRIBUTION OF UNITS FOR OUTPUT PULSE 1 Relative Frequency of Occurrence ∆ t w − Variation in Output Pulse − % VCC = 5 V TA = 25°C Median +0.5% Cext = 60 pF Rext = 10 kΩ TA = 25°C 0.5 tw ≈ 420 ns at VCC = 5 V 0 − 0.5 Median +0.5% −1 4.5 Median 4.75 5.5 VCC − Supply Voltage − V tw − Output Pulse Figure 3 Figure 4 VARIATION IN OUTPUT PULSE vs FREE-AIR TEMPERATURE OUTPUT PULSE vs TIMING RESISTOR VALUE 1 10 ms Cext = 1 µ F VCC = 5 V Cext = 60 pF Rext = 10 kΩ 1 ms Cext = 0.1 µ F 0.5 t w − Output Pulse ∆ t w − Variation in Output Pulse − % 5.25 5 tw ≈ 420 ns at TA = 25°C 0 100 µs Cext = 0.01 µ F 10 µs Cext = 1000 pF 1 µs Cext = 100 pF − 0.5 Cext = 10 pF 100 ns −1 −75 −50 VCC = 5 V TA = 25°C 10 ns −25 0 25 50 75 100 125 1 2 TA − Free-Air Temperature − °C See Note A 4 7 10 20 40 70 100 Rext − Timing Resistor Value − kΩ Figure 5 Figure 6 † Data for temperatures below 0°C and above 70°C, and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221 only. NOTE A: These values of resistance exceed the maximum recommended for use over the full military temperature range of the SN54221. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-8771101EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8771101EA SNJ54221J 76042012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 76042012A SNJ54LS 221FK 7604201EA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7604201EA SNJ54LS221J Samples 7604201FA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7604201FA SNJ54LS221W Samples JM38510/31402B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402B2A Samples JM38510/31402BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402BEA Samples JM38510/31402BFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402BFA Samples M38510/31402B2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402B2A Samples M38510/31402BEA ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402BEA Samples M38510/31402BFA ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31402BFA Samples SN54221J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54221J Samples SN54LS221J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54LS221J Samples SN74221N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74221N Samples SN74221NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74221N Samples SN74LS221D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS221 Samples SN74LS221DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS221 Samples SN74LS221DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS221 Samples Addendum-Page 1 Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LS221N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N Samples SN74LS221NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N Samples SN74LS221NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS221 Samples SNJ54221J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8771101EA SNJ54221J Samples SNJ54LS221FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 76042012A SNJ54LS 221FK SNJ54LS221J ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7604201EA SNJ54LS221J Samples SNJ54LS221W ACTIVE CFP W 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 7604201FA SNJ54LS221W Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of