SN74LV06APW

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 SNx4LV06A Hex Inverter Buffers/Drivers With Open-Drain Outputs 1 Features 2 Applications • • • • • • • • • • • 1 • • • • • • 2-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C Outputs are Disabled During Power Up and Power Down With Inputs Tied to VCC Support Mixed-Mode Voltage Operation on All Ports Ioff Supports Live insertion, Partial Power Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2500-V Human-Body Model (A114-1) – 200-V Machine Model (A115-A) – 2000-V Charged-Device Mode (C101) Servers Telecom Infrastructures TV Set-Top Boxes UPS Printers Elevators, and Escalators EPOS, ECR, and Cash Drawers Vending, Payment, Cash Machines 3 Description These hex inverter buffers/drivers are designed for 2V to 5.5-V VCC operation. The SN74LV06A device performs the Boolean function Y = A in positive logic. The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. Device Information(1) PART NUMBER PACKAGE SN74LV06A BODY SIZE (NOM) TVSOP (14) 3.60 mm x 4.40 mm SOIC (14) 8.65 mm × 3.91 mm SOP (14) 10.30 mm x 5.30 mm SSOP (14) 6.20 mm x 5.30 mm TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACER SPACER Simplified Schematic A Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 4 4 4 5 5 5 5 6 6 6 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, VCC = 2.5 V ± 0.2 V ........ Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ Switching Characteristics, VCC = 5 V ± 0.5 V ........... Noise Characteristics ................................................ Operating Characteristics........................................ Typical Characteristics ............................................ Parameter Measurement Information .................. 7 8 Detailed Description .............................................. 7 8.1 8.2 8.3 8.4 9 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 7 7 8 8 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application ................................................... 9 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 10 11.1 Layout Guidelines ................................................. 10 11.2 Layout Example .................................................... 10 12 Device and Documentation Support ................. 11 12.1 12.2 12.3 12.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 13 Mechanical, Packaging, and Orderable Information ........................................................... 11 4 Revision History Changes from Revision I (February 2015) to Revision J Page • Added TJ Junction temperature to the Absolute Maximum Ratings (1) table .......................................................................... 4 • Changed Figure 6 ................................................................................................................................................................ 10 Changes from Revision H (April 2005) to Revision I Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 • Changed datasheet title. ........................................................................................................................................................ 1 2 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 5 Pin Configuration and Functions (TOP VIEW) (TOP VIEW) NC - No internal connection Pin Functions PIN I/O DESCRIPTION NO. NAME 1 1A I Input 1 2 1Y O Output 1 3 2A I Input 2 4 2Y O Output 2 5 3A I Input 3 Output 3 6 3Y O 7 GND GND 8 4Y O Output 4 Ground Pin 9 4A I Input 4 10 5Y O Output 5 11 5A I Input 5 12 6Y O Output 6 Input 6 13 6A I 14 VCC — Power Pin Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback 3 SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC –35 mA ±50 mA 150 °C 150 °C Continuous current through VCC or GND Tstg Storage temperature range TJ Junction Temperature (1) (2) –65 UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±2000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN54LV06A (2) MIN VCC Supply voltage High level input voltage MAX MIN MAX 5.5 2 2 .5 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC = 2 V VIH SN74LV06A VCC = 2 V UNIT V V VCC × 0.7 0.5 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VIL Low level input voltage VI Input voltage 0 5.5 0 5.5 VO Output voltage 0 5.5 0 5.5 V 50 20 µA VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 8 8 VCC = 4.5 V to 5.5 V 16 16 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 20 VCC = 4.5 V to 5.5 V VCC × 0.3 VCC = 2 V IOL Low level output current Δt/Δv Input transition rise and fall rate VCC = 4.5 V to 5.5 V TA (1) (2) 4 Operating free-air temperature –55 125 V VCC × 0.3 –40 V mA ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Product Preview. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 6.4 Thermal Information SN74LV06A THERMAL METRIC (1) D DB DGV NS PW 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 100.6 112.5 135.2 95.4 128.7 RθJC(top) Junction-to-case (top) thermal resistance 51.8 65.0 57.9 52.9 57.2 RθJB Junction-to-board thermal resistance 54.9 59.9 68.3 51.2 70.7 ψJT Junction-to-top characterization parameter 25.0 25.0 9.2 17.9 9.3 ψJB Junction-to-board characterization parameter 54.7 59.3 67.6 53.8 70.0 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOL II –40°C to 85°C SN74LV06A SN74LV06A VCC TYP MAX MIN TYP –40°C to 125°C SN74LV06A UNIT MAX IOL = 50 µA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 0.4 IOL = 8 mA 3V 0.44 0.44 0.44 IOL = 16 mA 4.5 V 0.55 0.55 0.55 VI = 5.5 V or GND 0 to 5.5 V IOH VI = VIL, VOH = VCC ICC VI = VCC or GND, IO = 0 Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND 0.1 V ±1 ±1 ±1 µA 5.5 V ±2.5 ±2.5 ±2.5 µA 5.5 V 20 20 20 µA 0 5 5 5 µA 3.3 V 1.6 1.6 1.6 pF 6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A Y CL = 15 pF tPLH A Y tPHL A Y PARAMETER tPLH tPHL (1) –40°C to 85°C SN74LV06A TA = 25°C MIN CL = 50 pF –40°C to 125°C SN74LV06A UNIT TYP MAX MIN MAX MIN MAX 5.4 (1) 10.4 (1) 1 (1) 13 (1) 1 14 7.2 (1) 10.4 (1) 1 (1) 13 (1) 1 14 9.7 15.2 1 18 1 19 9.3 15.2 1 18 1 19 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tPLH (1) FROM (INPUT) TO (OUTPUT) A Y tPHL A Y tPLH A Y tPHL A Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF –40°C to 85°C SN74LV06A TA = 25°C MIN –40°C to 125°C SN74LV06A UNIT TYP MAX MIN MAX MIN MAX 4.1 (1) 7.1 (1) 1 (1) 8.5 (1) 1 9.5 (1) (1) (1) (1) 1 9.5 4.9 7.1 1 8.5 7.1 10.6 1 12 1 13 6.4 10.6 1 12 1 13 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback 5 SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 www.ti.com 6.8 Switching Characteristics, VCC = 5 V ± 0.5 V operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER tPLH (1) FROM (INPUT) TO (OUTPUT) A Y tPHL A Y tPLH A Y tPHL A Y –40°C to 85°C SN74LV06A TA = 25°C LOAD CAPACITANCE MIN CL = 15 pF UNIT TYP MAX MIN MAX MIN MAX 3 (1) 5.5 (1) 1 (1) 6.5 (1) 1 7 (1) (1) (1) 6.5 (1) 1 7 3.3 CL = 50 pF –40°C to 125°C SN74LV06A 5.5 1 4.8 7.5 1 8.5 1 9 4.4 7.5 1 8.5 1 9 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 6.9 Noise Characteristics (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C TYP MAX VOL(P) Quiet output, maximum dynamic VOL PARAMETER 0.5 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.1 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.3 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) MIN UNIT V 2.31 V 0.99 V UNIT Characteristics are for surface-mount packages only. 6.10 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, f = 10 MHz VCC TYP 3.3 V 2.6 5V 4.7 pF 6.11 Typical Characteristics 4 7 3.5 6 3 5 2.5 TPD (ns) TPD (ms) TPD in ns 2 4 3 1.5 2 1 1 0.5 TPD in ns 0 -100 -50 0 50 Temperature (qC) 100 D001 Figure 1. TPD vs Temperature at 5 V 6 Submit Documentation Feedback 0 150 0 1 2 3 VCC (V) 4 5 6 D002 Figure 2. TPD vs VCC at 25°C Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 7 Parameter Measurement Information VCC VCC RL = 1 kΩ From Output Under Test 50% VCC Input Test Point 50% VCC tPHL CL (see Note A) 0V tPLH ≈VCC 50% VCC Output VOL + 0.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES LOAD CIRCUIT FOR OPEN-DRAIN OUTPUTS A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 3. Load Circuit and Voltage Waveforms 8 Detailed Description 8.1 Overview These hex inverter buffers/drivers are designed for 2-V to 5.5-V VCC operation. The SN74LV06A device performs the Boolean function Y = A in positive logic. The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current back-flow through the devices when they are powered down. 8.2 Functional Block Diagram A Y Figure 4. Logic Diagram (Positive Logic) Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback 7 SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 www.ti.com 8.3 Feature Description • • • Wide operating voltage range – Operates from 2 V to 5.5 V Allows up or down voltage translation – Inputs and outputs accept voltages to 5.5 V Ioff feature – Allows voltages on the inputs and outputs when VCC is 0 V 8.4 Device Functional Modes Table 1. Function Table (Each Inverter) INPUT A 8 Submit Documentation Feedback OUTPUT Y H L L H Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74LV06A is a low drive Open drain CMOS device that can be used for a multitude of buffer type functions. The inputs are 5.5 V tolerant and the outputs open drain and 5.5 V tolerant allowing it to translate up to 5.5 V or down to any other voltage between GND and 5.5 V. 9.2 Typical Application Buffer Function Basic LED Driver VPU uC or Logic LV06A VPU Wired OR uC or Logic uC or Logic LV06A uC or Logic LV06A Figure 5. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and is open drain so it has low output drive only. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The parallel output drive can create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions: – For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table. – For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommended Output Conditions: – Load currents should not exceed 35 mA per output and 50 mA total for the part. Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback 9 SN54LV06A, SN74LV06A SCES336J – MAY 2000 – REVISED JANUARY 2016 www.ti.com Typical Application (continued) 9.2.3 Application Curves 3.5 VOUT input low VOUT input high 3 VOUT (V) 2.5 2 1.5 1 0.5 0 -0.5 0 1 2 VCC (V) 3 4 D003 Figure 6. Output During Power Up with 4 k Pull-up at 3.3 V 10 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF capacitor is recommended for each power terminal. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1 μF and 1 μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. It is generally OK to float outputs unless the part is a transceiver. 11.2 Layout Example Vcc Unused Input Input Output Output Unused Input Input Figure 7. Layout Diagram 10 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A SN54LV06A, SN74LV06A www.ti.com SCES336J – MAY 2000 – REVISED JANUARY 2016 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LV06A Click here Click here Click here Click here Click here SN74LV06A Click here Click here Click here Click here Click here 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: SN54LV06A SN74LV06A Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV06AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06ADGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06ADRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV06A SN74LV06APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A SN74LV06APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV06A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of