SN74LV10ANSR

SN74LV10A SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 SN74LV10A Triple 3-Input Positive-NAND Gate 1 Features 2 Description • • • These triple 3-input positive-NAND designed for 2-V to 5.5-V VCC operation. • • • 2-V to 5.5-V VCC Operation Max tpd of 7 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II gates are The SN74LV10A devices perform the Boolean function Y = A • B • C in positive logic. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Device Information PART NUMBER SN74LV10A (1) PACKAGE(1) BODY SIZE (NOM) D (SOIC, 14) 8.65 mm x 3.90 mm NS (SO, 14) 10.20 mm x 5.30 mm PW (TSSOP, 14) 5.00 mm x 4.40 mm For all available packages, see the orderable addendum at the end of the data sheet. xA xB xY xC Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 ESD Ratings............................................................... 4 5.3 Recommended Operating Conditions ........................4 5.4 Thermal Information....................................................5 5.5 Electrical Characteristics.............................................5 5.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........5 5.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6 5.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............6 5.9 Noise Characteristics.................................................. 6 5.10 Operating Characteristics......................................... 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Documentation Support.......................................... 10 10.2 Receiving Notification of Documentation Updates..10 10.3 Support Resources................................................. 10 10.4 Trademarks............................................................. 10 10.5 Electrostatic Discharge Caution..............................10 10.6 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2015) to Revision F (May 2022) Page • Updated the numbering, formatting, tables, figures and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 4 Pin Configuration and Functions 1A 1 14 VCC 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y Figure 4-1. SN74LV10A . . . D, NS, OR PW PACKAGE (TOP VIEW) PIN NAME NO. TYPE(1) DESCRIPTION 1A 1 I 1A Input 1B 2 I 1B Input 2A 3 I 2A Input 2B 4 I 2B Input 2C 5 I 2C Input 2Y 6 O 2Y Output 3Y 8 O 3Y Output 3A 9 I 3A Input 3B 10 I 3B Input 3C 11 I 3C Input 1Y 12 O 1Y Output 1C 13 I 1C Input GND 7 — Ground Pin VCC 14 — Power Pin (1) Signal Types: I = Input, O = Output. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A 3 SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX Supply voltage range –0.5 7 V range(2) –0.5 7 V –0.5 VCC + 0.5 V VI Input voltage VO Output voltage range applied in high or low state(2) (3) state(2) –0.5 UNIT VO Output voltage range applied in power-off IIK Input clamp current (VI < 0) –20 7 mA V IOK Output clamp current (VO < 0) –50 mA IO Continuous output current (VO = 0 to VCC) ±25 mA Continuous current through VCC or GND ±50 mA θJA Package thermal impedance 150 °C Tstg Storage temperature 150 °C (1) (2) (3) –65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. 5.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) Electrostatic discharge (1) (1) (2) ± 2000 Machine Model, per JEDEC specification ± 200 Charged device model (CDM), per JEDEC specification JS-002 UNIT (2) V ± 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC (1) Supply voltage VCC = 2 V VIH High level input voltage MIN MAX 2 5.5 Low level input voltage VI Input voltage VO Output voltage VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 0.5 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V IOH High level output current VCC × 0.3 5.5 0 VCC V –50 µA –2 VCC = 3 V to 3.6 V –6 Submit Document Feedback V 0 VCC = 2.3 V to 2.7 V VCC = 4.5 V to 5.5 V 4 V VCC = 2.3 V to 2.7 V VCC = 2 V V 1.5 VCC = 2.3 V to 2.7 V VCC = 2 V VIL UNIT V mA –12 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 5.3 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VCC = 2 V IOL Low level output current Δt/Δv Input transition rise and fall rate VCC = 2.3 V to 2.7 V 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA µA mA ns/V 20 Operating free-air temperature (1) UNIT 50 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004 5.4 Thermal Information SN74LV10A THERMAL METRIC(1) RθJA (1) D NS PW 14 PINS 14 PINS 14 PINS 86 76 113 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 5.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS High-level output voltage VCC MIN IOH = –50 µA 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –6 mA 3V 2.48 4.5 V 3.8 IOH = –12 mA TYP MAX 2 V IOL = 50 µA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 4.5 V 0.55 VOL Low-level output voltage II Input leakage current VI = 5.5 V or GND ICC Ci IOL = 12 mA UNIT VCC - 0.1 0.1 V 0 to 5.5 V ±1 µA Supply current VI = VCC I =0 or GND, O 5.5 V 20 µA Input capacitance VI = VCC or GND 3.3 V 1.9 pF 5.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A, B, or C Y CL = 15 pF tpd A, B, or C Y CL = 50 pF TA = 25°C MIN TYP SN74LV10A MAX MIN MAX 7.1 13 1 15.5 10.3 17.1 1 20.5 UNIT ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A 5 SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 5.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (seeFigure 6-1 ) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A, B, or C Y CL = 15 pF tpd A, B, or C Y CL = 50 pF TA = 25°C MIN TYP SN74LV10A MAX MIN MAX 5.2 8.4 1 10 7.4 11.9 1 13.5 UNIT ns 5.8 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A, B, or C Y tpd A, B, or C Y TA = 25°C MIN SN74LV10A TYP MAX MIN MAX CL = 15 pF 3.9 5.9 1 7 CL = 50 pF 5.4 7.9 1 9 UNIT ns 5.9 Noise Characteristics VCC = 3.3 V, CL = 50 pF, TA = 25°C PARAMETER(1) TYP MAX 0.2 0.8 V Quiet output, minimum dynamic VOL 0 –0.8 V Quiet output, minimum dynamic VOH 3.2 VOL(P) Quiet output, maximum dynamic VOL VOL(V) VOH(V) VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) MIN UNIT V 2.31 V 0.99 V TYP UNIT Characteristics are for surface-mount packages only. 5.10 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, Submit Document Feedback f = 10 MHz VCC 3.3 V 5V 14 16.7 pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 6 Parameter Measurement Information Figure 6-1. Load Circuit and Voltage Waveforms A. B. C. D. E. F. G. H. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. The outputs are measured one at a time, with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPHL and tPLH are the same as tpd. All parameters and waveforms are not applicable to all devices. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A 7 SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 7 Detailed Description 7.1 Overview These triple 3-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation. The SN74LV10A devices perform the Boolean function Y = A • B • C in positive logic. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. 7.2 Functional Block Diagram xA xB xY xC Figure 7-1. logic diagram, each gate (positive logic) 7.3 Device Functional Modes Table 7-1. FUNCTION TABLE (each gate) INPUT(1) (1) (2) 8 OUTPUT (2) A B C H H H L L X X H X L X H X X L H Y H = High Voltage Level, L = Low Voltage Level, X = Don't Care H = Driving High, L = Driving Low Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A 9 SN74LV10A www.ti.com SCES338F – SEPTEMBER 2000 – REVISED MAY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV10A PACKAGE OPTION ADDENDUM www.ti.com 25-May-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV10AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples SN74LV10ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples SN74LV10ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples SN74LV10ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV10A Samples SN74LV10APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples SN74LV10APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples SN74LV10APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV10A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of