SN74LV125ATNSR

SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FEATURES • • • • • • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 3.8 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports • • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) XXXX XXXX 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y VCC 14 2 1 14 2 13 4OE 3 12 4A 4 11 4Y 5 6 10 3OE 9 3A 7 8 3Y 1 GND 1OE 1A 1Y 2OE 2A 2Y GND 1OE RGY PACKAGE (TOP VIEW) D, DB, NS, OR PW PACKAGE (TOP VIEW) DESCRIPTION/ORDERING INFORMATION The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA QFN – RGY SOIC – D SOP – NS –40°C to 85°C SSOP – DB TSSOP – PW (1) ORDERABLE PART NUMBER Reel of 1000 SN74LV125ATRGYR Tube of 50 SN74LV125ATD Reel of 2500 SN74LV125ATDR Tube of 50 SN74LV125ATNS Reel of 2000 SN74LV125ATNSR Tube of 80 SN74LV125ATDB Reel of 2000 SN74LV125ATDBR Tube of 90 SN74LV125ATPW Reel of 2000 SN74LV125ATPWR Reel of 250 SN74LV125ATPWT TOP-SIDE MARKING VV125 LV125AT Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A 1 2 3OE 3 1Y 3A 8 9 3Y 13 4 4OE 2OE 2A 10 5 6 2Y 4A 11 12 4Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V VO Output voltage range (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±50 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA Continuous current through VCC or GND θJA Package thermal impedance D package (4) 86 DB package (4) 96 package (4) 76 PW package (4) 113 NS RGY package (5) Tstg (1) (2) (3) (4) (5) 2 Storage temperature range °C/W 47 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V VI Input voltage MIN MAX 4.5 5.5 UNIT V 2 V 0.8 V V 0 5.5 High or low state 0 VCC 3-state 0 5.5 VO Output voltage IOH High-level output current VCC = 4.5 V to 5.5 V –16 IOL Low-level output current VCC = 4.5 V to 5.5 V 16 mA ∆t/∆v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 ns/V TA Operating free-air temperature 125 °C (1) –40 V mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VCC TA = –40°C to 85°C TA = 25°C MIN TYP 4.5 IOH = –50 µA 4.5 V 4.4 IOH = –16 mA 4.5 V 3.8 IOL = 50 µA 4.5 V IOL = 16 mA 4.5 V MAX 0 MIN TA = –40°C to 125°C MAX MIN 4.4 4.4 3.8 3.8 UNIT MAX V 0.1 0.1 0.1 0.55 0.55 0.55 V II VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA 0 0.5 5 5 µA ∆ICC (1) TEST CONDITIONS (1) Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND 2 pF This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A Y ten OE Y tdis OE tpd ten tdis OE PARAMETER tsk(o) TA = –40°C to 85°C TA = 25°C TA = –40°C to 125°C UNIT MIN TYP MAX MIN MAX MIN MAX CL = 15 pF 1.9 3.8 5.5 1 6.5 1 8.5 ns CL = 15 pF 2 3.6 5.1 1 6 1 7.5 ns Y CL = 15 pF 1.5 3.2 6.8 1 8 1 10 ns A Y CL = 50 pF 2.9 5.3 7.5 1 8.5 1 10.5 ns OE Y CL = 50 pF 2.8 5.1 7.1 1 8 1 9.5 ns Y CL = 50 pF 2.8 6.1 8.8 1 10 1 10 ns 1 ns CL = 50 pF 1 1 3 SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 Noise Characteristics (1) VCC = 5 V, CL = 50 pF, TA = 25°C TYP MAX VOL(P) Quiet output, maximum dynamic VOL MIN 1.1 1.5 V VOL(V) Quiet output, minimum dynamic VOL –0.3 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 3 UNIT V 2 V 0.8 V Characteristics are for surface-mount packages only. Operating Characteristics VCC = 5 V, TA - 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS Outputs enabled CL = 50 pF, f = 10 MHz TYP 16 UNIT pF SN74LV125AT QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES629A – MAY 2005 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV125ATD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATDBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATPWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV125AT SN74LV125ATRGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 VV125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of