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SN54LV126A, SN74LV126A
SCES131I – MARCH 1998 – REVISED FEBRUARY 2015
SNx4LV126A Quadruple Bus Buffer Gates With 3-State Outputs
1 Features
3 Description
•
•
•
The ‘LV126A quadruple bus buffer gates are
designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) 2.3 V at
VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Support Mixed-Mode Voltage Operation on All
Ports
Latch-Up Performance Exceeds 250 mA per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
These quadruple bus buffer gates are designed for 2V to 5.5-V VCC operation.
The ’LV126A devices feature independent line drivers
with 3-state outputs. Each output is disabled when
the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Device Information(1)
PART NUMBER
SN74LV126A
2 Applications
•
•
•
•
•
Servers
Network Switch
Electronic Point of Sales
TV
Set-Top-Box
PACKAGE
BODY SIZE (NOM)
SOIC (14)
3.91 mm × 8.65 mm
SOP (14)
5.30 mm × 10.30 mm
SSOP (14)
5.30 mm × 6.20 mm
TSSOP (14)
4.40 mm × 5.00 mm
TVSOP (14)
4.40 mm × 3.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1OE
1A
2OE
2A
1
2
3OE
3
1Y
4
5
3A
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV126A, SN74LV126A
SCES131I – MARCH 1998 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ±0.2 V .........
Switching Characteristics, VCC = 3.3 V ±0.3 V .........
Switching Characteristics, VCC = 5 V ±0.5 V ............
Noise Characteristics for SN74LV126A ....................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
Changes from Revision H (April 2005) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated operating free-air temperature maximum from 85°C to 125°C for SN74LV126A ................................................... 5
2
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SCES131I – MARCH 1998 – REVISED FEBRUARY 2015
5 Pin Configuration and Functions
SN54LV126A: J or W Package
SN74LV126A: D, DB, DGV, NS, or PW Package
(Top View)
14
2
13
3
12
4
11
5
10
6
9
7
8
1A
1OE
NC
VCC
4OE
1
VCC
4OE
4A
4Y
3OE
3A
3Y
1Y
NC
2OE
NC
2A
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
2Y
GND
NC
3Y
3A
1OE
1A
1Y
2OE
2A
2Y
GND
SN54LV126A: FK Package
(Top View)
A.
NC − No internal connection
Pin Functions
PIN
I/O
1
1OE
DESCRIPTION
2
1A
Input 1
3
1Y
Output 1
4
2OE
Enable 2
5
2A
Input 2
6
2Y
Output 2
7
GND
8
3Y
Output 3
Input 3
Enable pin
GND
9
3A
10
3OE
Enable 3
11
4Y
Output 4
12
4A
Input 4
13
4OE
Enable 4
14
VCC
VCC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2) (3)
–0.5
VCC + 0.5 V
V
IIK
Input clamp current, VI < 0
–20
mA
IOK
Output clamp current, VO < 0
–50
mA
IO
Continuous output current, VO = 0 to VCC
–35
35
mA
Continuous current through VCC or GND
–70
70
mA
Storage temperature
–65
150
°C
Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
see
VCC
(1)
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
VI
VO
Low-level input voltage
VCC = 2.3 to 2.7 V
VCC × 0.7
VCC = 3 to 3.6 V
VCC × 0.7
VCC = 4.5 to 5.5 V
VCC × 0.7
0.5
VCC × 0.3
VCC = 3 to 3.6 V
VCC × 0.3
VCC = 4.5 to 5.5 V
VCC × 0.3
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2 V
IOH
High-level output current
4
V
V
V
–50
VCC = 2.3 to 2.7 V
–2
VCC = 3 to 3.6 V
–8
VCC = 4.5 to 5.5 V
(1)
V
VCC = 2.3 to 2.7 V
Input voltage
Output voltage
V
1.5
VCC = 2 V
VIL
UNIT
µA
mA
–16
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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Recommended Operating Conditions (continued)
see (1)
MIN
MAX
VCC = 2 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
50
VCC = 2.3 to 2.7 V
2
VCC = 3 to 3.6 V
8
VCC = 4.5 to 5.5 V
16
VCC = 2.3 to 2.7 V
200
VCC = 3 to 3.6 V
100
VCC = 4.5 to 5.5 V
TA
Operating free-air temperature
UNIT
µA
mA
ns/V
20
SN54LV126A
–55
125
SN74LV126A
–40
125
°C
6.4 Thermal Information
D
THERMAL METRIC (1)
DB
DGV
NS
PW
RθJA
Junction-to-ambient thermal resistance (2)
92.7
105.0
127.6
89.6
119.8
RθJC(top)
Junction-to-case (top) thermal resistance
54.1
57.5
50.7
47.2
48.6
RθJB
Junction-to-board thermal resistance
47.0
52.3
60.5
48.4
61.5
ψJT
Junction-to-top characterization parameter
18.9
19.1
6.1
14.0
5.7
ψJB
Junction-to-board characterization parameter
46.7
51.8
59.8
48.1
61.0
(1)
(2)
UNIT
14 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = –50 µA
2 to 5.5 V
IOH = –2 mA
2.3 V
IOH = –8 mA
3V
IOH = –16 mA
4.5 V
IOL = 50 µA
2 to 5.5 V
IOL = 2 mA
2.3 V
IOL = 8 mA
3V
0.44
IOL = 16 mA
4.5 V
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
±1
µA
IOZ
VO = VCC or GND
5.5 V
±5
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
µA
Ci
VI = VCC or GND
3.3 V
VOH
VOL
VCC – 0.1
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2
V
2.48
3.8
0.1
0.4
1.6
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V
pF
5
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SCES131I – MARCH 1998 – REVISED FEBRUARY 2015
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6.6 Switching Characteristics, VCC = 2.5 V ±0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM (INPUT)
TO (OUTPUT)
LOAD
CAPACITANCE
TA = 25°C
MIN
A
ten
OE
tdis
OE
tpd
A
ten
OE
tdis
OE
Y
Y
CL = 15 pF
MAX UNIT
MAX
7.1 (1)
13 (1)
1 (2)
15.5 (2)
(1)
(1)
(2)
15.5 (2)
7.4
13
1
5.7 (1)
14.7 (1)
1 (2)
17 (2)
9.2
16.5
1
18.5
9.5
16.5
1
18.5
8.1
18.2
15
20.5
CL = 50 pF
tsk(o)
(1)
(2)
(3)
MIN
TYP
ns
ns
2 (3)
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV126A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
Value applies for SN74LV126A only
6.7 Switching Characteristics, VCC = 3.3 V ±0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM (INPUT)
tpd
A
ten
OE
tdis
OE
tpd
A
ten
OE
tdis
OE
TO (OUTPUT)
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 15 pF
MIN
MAX UNIT
8 (1)
1 (2)
9.5 (2)
5.1 (1)
8 (1)
1 (2)
9.5 (2)
(1)
(1)
(2)
(2)
TYP
MAX
5 (1)
4.4
Y
CL = 50 pF
1
11.5
11.5
1
13
6.6
11.5
1
13
6.1
13.2
1
15
tsk(o)
(1)
(2)
(3)
9.7
6.4
ns
ns
1.5 (3)
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV126A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
Value applies for SN74LV126A only
6.8 Switching Characteristics, VCC = 5 V ±0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM (INPUT)
tpd
A
ten
OE
tdis
TO (OUTPUT)
Y
LOAD
CAPACITANCE
CL = 15 pF
OE
tpd
A
ten
OE
tdis
OE
TA = 25°C
MIN
MIN
MAX UNIT
5.5 (1)
1 (2)
6.5 (2)
3.6 (1)
5.1 (1)
1 (2)
6 (2)
(1)
(1)
(2)
8 (2)
TYP
MAX
3.5 (1)
3.3
Y
CL = 50 pF
tsk(o)
(1)
(2)
(3)
6
6.8
1
4.6
7.5
1
8.5
4.6
7.1
1
8
4.3
8.8
1
10
1
ns
ns
1 (3)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV126A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
This values applies for SN74LV126A only
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6.9 Noise Characteristics for SN74LV126A
VCC = 3.3 V, CL = 50 pF, TA = 25°C (see
(1)
)
PARAMETER
MIN
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.3
0.8
VOL(V)
Quiet output, minimum dynamic VOL
–0.2
–0.8
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.1
UNIT
V
2.31
0.97
Characteristics are for surface-mount packages only.
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
Outputs enable; CL = 50 pF, ƒ = 10 MHz
VCC
TYP
3.3 V
14.4
5V
15.9
UNIT
pF
6.11 Typical Characteristics
TBD
7
8
6
7
6
5
tpd (ns)
tpd (ns)
5
4
3
4
3
2
2
1
1
0
-100
0
-50
0
50
Temperature (°C)
100
150
0
1
D001
Figure 1. SN74LV126A tPD vs Temperature at 5 V
2
3
VCC (V)
4
5
6
D002
Figure 2. SN74LV126A tPD vs VCC at 25°C
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7 Parameter Measurement Information
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
VOH
50% VCC
VOL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
VCC
Output
Control
≈VCC
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
50% VCC
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
Figure 3. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LV126A devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective
gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver.
8.2 Functional Block Diagram
1OE
1A
2OE
2A
A.
1
3OE
2
3
1Y
3A
4
4OE
5
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
•
•
•
Wide operating voltage range, operates from 2 to 5.5 V
Allows down voltage translation, inputs accept voltages to 5.5 V
Ioff supports live insertion, partial power down mode, and back drive protection
8.4 Device Functional Modes
Table 1. Function Table
(Each Buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV126A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates minimize overshoot and undershoot on the
outputs. The inputs are 5.5-V tolerant at any valid VCC making Ideal for translating down to VCC.
9.2 Typical Application
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions.
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions.
2. Recommend output conditions
– Load currents should not exceed 35 mA per output and 70 mA total for the part
– Outputs should not be pulled above VCC
10
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Typical Application (continued)
9.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in Recommended
Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For
devices with a single supply, 0.1 μF is recommended and if there are multiple VCC terminals then .01 or .022 μF
is recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1 and 1 μF are commonly used in parallel. The bypass capacitor should be installed as
close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IOs so they also cannot float when disabled.
11.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Recommendation
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Product Folder Links: SN54LV126A SN74LV126A
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11
SN54LV126A, SN74LV126A
SCES131I – MARCH 1998 – REVISED FEBRUARY 2015
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV126A
Click here
Click here
Click here
Click here
Click here
SN74LV126A
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV126A SN74LV126A
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LV126AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV126A
SN74LV126APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
SN74LV126APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV126A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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