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SN54LV132A, SN74LV132A
SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
1 Features
3 Description
•
•
•
The 'LV132A devices are quadruple positive-NAND
gates designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 9 ns at 5 V
Typical VOLP (Output Ground Bounce) 2.3 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Latch-Up Performance Exceeds 250 mA per
JESD 17
Ioff Supports Live Insertion, Partial Power-Down
Mode, and Back Drive Protection
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The 'LV132A devices perform the Boolean function Y
= A • B or Y = A + B in positive logic.
Each circuit functions as a NAND gate, but because
of the Schmitt trigger, it has different input threshold
levels for positive- and negative-going signals.
These circuits are temperature compensated and can
be triggered from the slowest of input ramps and still
give clean jitter-free output signals.
Device Information(1)
PART NUMBER
LV132A
2 Applications
•
•
•
•
•
Industrial PC: Rugged PC and Laptop
Access Control and Security: Camera
Surveillance IP Network
Vending, Payment and Change Machines
Patient Monitoring STB / DVR / Streaming Media
(Withdraw)
Other Motor Drives (Such as Switch Reluctance)
PACKAGE
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
SOP (14)
10.30 mm × 5.30
mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
TVSOP (14)
3.60 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Logic Diagram (Positive Logic)
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV132A, SN74LV132A
SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Logic Diagram (Positive Logic) ............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
4
5
5
6
6
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Noise Characteristics for SN74LV132A ....................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision I (June 2010) to Revision J
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated operating free-air temperature maximum from 85°C to 125°C for SN74LV126A ................................................... 4
2
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SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
SN54LV132A: J or W Package
SN74LV132A: D, DB, DGV, NS, or PW Package
(Top View)
14
2
13
3
12
4
11
5
10
6
9
7
8
1B
1A
NC
VCC
4B
1
V CC
4B
4A
4Y
3B
3A
3Y
3 2
1Y
NC
2A
NC
2B
4
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
SN54LV132A: FK Package
(Top View)
A.
NC - No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
1A
I
1A input
2
1B
I
1B
3
1Y
O
1Y
4
2A
I
2A
5
2B
I
2B
6
2Y
O
2Y
7
GND
—
GND
8
3Y
O
3Y
9
3A
I
3A
10
3B
I
3B
11
4Y
O
4Y
12
4A
I
4A
13
4B
I
4B
14
VCC
—
VCC
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
25
mA
Tstg
(1)
(2)
(3)
(3)
–25
Continuous current through VCC or GND
–50
50
mA
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value is limited to 5.5-V maximum.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (A115-A)
(1)
(2)
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
See
(1) (2)
MIN
MAX
VCC
Supply voltage
2
5.5
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
–50
μA
VCC = 2 V
IOH
High-level output current
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Low-level output current
50
VCC = 2.3 V to 2.7 V
(1)
(2)
4
Operating free-air temperature
μA
2
VCC = 3 V to 3.6 V
6
VCC = 4.5 V to 5.5 V
TA
mA
–12
VCC = 2 V
IOL
UNIT
mA
12
SN54LV132A
–55
125
SN74LV132A
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
D
THERMAL METRIC (1)
DB
DGV
NS
PW
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
90.6
107.1
129.0
90.7
122.6
RθJC(top)
Junction-to-case (top) thermal resistance
50.9
59.6
52.1
48.3
51.4
RθJB
Junction-to-board thermal resistance
44.8
54.4
62.0
49.4
64.4
ψJT
Junction-to-top characterization parameter
14.7
20.5
6.5
14.6
6.7
ψJB
Junction-to-board characterization parameter
44.5
53.8
61.3
49.1
63.8
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VT+
VT–
ΔVT
VOH
TEST CONDITIONS
Positive-going input
threshold voltage
Negative-going input
threshold voltage
Hysteresis
(VT+ − VT−)
SN54LV132A (1)
MIN
TYP
SN74LV132A
MAX
MIN
TYP
MAX
2.5 V
1
1.75
1
1.75
3.3 V
1.31
2.31
1.31
2.31
5V
1.95
3.5
1.95
3.5
2.5 V
0.75
1.5
0.75
1.5
3.3 V
0.99
2.07
0.99
2.07
5V
1.5
3.05
1.5
3.05
2.5 V
0.25
1
0.25
1
3.3 V
0.33
1.32
0.33
1.32
5V
0.5
2
0.5
2
IOH = –50 μA
2 to 5.5 V
IOH = –2 mA
2.3 V
IOH = –6 mA
IOH = –12 mA
VOL
VCC
VCC – 0.1
VCC – 0.1
2
2
3V
2.48
2.48
4.5 V
3.8
UNIT
V
V
V
V
3.8
IOL = 50 μA
2 to 5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
IOL = 12 mA
4.5 V
0.55
0.55
0.1
0.1
V
II
VI = 5.5 V or GND
0 to 5.5 V
±1
±1
μA
ICC
VI = VCC or GND, IO
=0
5.5 V
20
20
μA
Ioff
VI or VO = 0 to 5.5 V
0V
5
5
μA
Ci
VI = VCC or GND
(1)
3.3 V
1.9
1.9
pF
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7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
FROM (INPUT)
TO (OUTPUT)
A or B
Y
LOAD
CAPACITANCE
SN54LV132A (1)
TA = 25°C
MIN
SN74LV132A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
7.9 (2)
16.5 (2)
1 (2)
18.5 (2)
1
18.5
CL = 50 pF
10.8
20.2
1
23
1
23
UNIT
ns
SN54LV132A is in product preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
FROM (INPUT)
TO (OUTPUT)
A or B
Y
LOAD
CAPACITANCE
SN54LV132A (1)
TA = 25°C
MIN
SN74LV132A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
5.6 (2)
11.9 (2)
1 (2)
14 (2)
1
14
CL = 50 pF
7.6
15.4
1
17.5
1
17.5
UNIT
ns
SN54LV132A is in product preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
(2)
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
SN54LV132A (1)
TA = 25°C
MIN
SN74LV132A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
3.9 (2)
7.7 (2)
1 (2)
9 (2)
1
9
CL = 50 pF
5.3
9.7
1
11
1
11
MIN
UNIT
ns
SN54LV132A is in product preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.9 Noise Characteristics for SN74LV132A
VCC = 3.3 V, CL = 50 pF, TA = 25°C (1)
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
PARAMETER
0.21
0.8
VOL(V)
Quiet output, minimum dynamic VOL
–0.09
–0.8
VOH(V)
Quiet output, minimum dynamic VOH
3.12
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
UNIT
V
2.31
0.99
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
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TEST CONDITIONS
CL = 50 pF, f = 10 MHz
VCC
TYP
3.3 V
7.5
5V
11.2
UNIT
pF
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SCLS394J – APRIL 1999 – REVISED FEBRUARY 2015
7.11 Typical Characteristics
7
9
8
6
7
5
tpd (ns)
tpd (ns)
6
4
3
5
4
3
2
2
1
0
-100
1
0
-50
0
50
Temperature (°C)
100
150
0
1
2
D001
Figure 1. SN74LV132A tpd vs Temperature
3
VCC (V)
4
5
6
D002
Figure 2. SN74LV132A tpd vs VCC
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8 Parameter Measurement Information
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
VOH
50% VCC
VOL
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLZ
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
50% VCC
tPZL
tPHL
tPLH
In-Phase
Output
0V
VCC
Output
Control
50% VCC
VOH
0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SN74LV132A Is a quadruple 2-input positive NAND gate with low drive that produces slow rise and fall
times. This reduces ringing on the output signal. Each circuit functions as a NAND gate, but because of the
Schmitt trigger, it has different input threshold levels for positive- and negative-going signals. These circuits are
temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free
output signals.
9.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
Wide operating voltage range, operates from 2 to 5.5 V
Allows down voltage translation, inputs accept voltages to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUT
Y
A
B
H
H
L
L
X
H
X
L
H
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV132A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.
10.2 Typical Application
5-V Accessory
5-V Regulated
0.1 PF
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing. The Schmitt trigger
inputs allow for slow or noisy inputs while producing clean outputs.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC
10
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Typical Application (continued)
10.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in Recommended
Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1 μF and if there are multiple VCC terminals then TI recommends .01 μF or .022 μF for
each power terminal. It is okay to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal
as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output
enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of
the IOs so they also cannot float when disabled.
12.2 Layout Example
VCC
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Layout Recommendation
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV132A
Click here
Click here
Click here
Click here
Click here
SN74LV132A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV132AD
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132ADBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132ADGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132ADR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132ADRE4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132ANSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV132A
Samples
SN74LV132APW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132APWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132APWRG4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
SN74LV132APWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV132A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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