SN74LV138ABQBR

SN74LV138A SCLS395N – APRIL 1998 – REVISED MARCH 2023 SN74LV138A 3-Line to 8-Line Decoders or Demultiplexers 1 Features 3 Description • • • The SN74LV138A device is 3-line to 8-line decoders/ demultiplexers designed for 2 V to 5.5 V VCC operation. • • • • VCC operation of 2 V to 5.5 V Maximum tpd of 9.5 ns at 5 V Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support mixed-mode voltage operation on all ports Ioff supports partial-power-down mode operation Latch-up performance exceeds 250 mA per JESD 17 2 Applications • • • • Output expansion LED matrix control 7-segment display control 8-bit data storage The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding. Package Information PART NUMBER SN74LV138A (1) PACKAGE(1) BODY SIZE D (SOIC, 16) 9.90 mm × 3.91 mm DB (SSOP, 16) 6.20 mm × 5.30 mm DGV (TVSOP, 16) 3.60 mm × 4.40 mm NSA (BGA, 16) 2.00 mm × 2.00 mm PW (TSSOP, 16) 5.00 mm × 4.40 mm RGY (VQFN, 16) 4.00 mm × 3.50 mm BQB (WQFN, 16) 3.60 mm × 2.60 mm For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 Logic Diagram (Positive Logic) 2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 3 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions(1) .................... 6 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................6 6.6 Switching Characteristics, VCC = 2.5 V ± 0.25 V.........7 6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........7 6.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............7 6.9 Operating Characteristics........................................... 8 6.10 Typical Characteristics.............................................. 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Application.................................................... 13 9.3 Power Supply Recommendations.............................16 9.4 Layout....................................................................... 16 10 Device and Documentation Support..........................17 10.1 Documentation Support.......................................... 17 10.2 Receiving Notification of Documentation Updates..17 10.3 Support Resources................................................. 17 10.4 Trademarks............................................................. 17 10.5 Electrostatic Discharge Caution..............................17 10.6 Glossary..................................................................17 11 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History Changes from Revision M (December 2022) to Revision N (March 2023) Page • Updated the structural layout of document to current standard..........................................................................1 Changes from Revision L (August 2005) to Revision M (December 2022) Page • Updated the numbering, formatting, tables, figures and cross-references throughout the document to reflect modern datasheet standards.............................................................................................................................. 1 • Added the Applications section...........................................................................................................................1 • Added the Device Information table and removed the Ordering Information table.............................................1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 3 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 5 Pin Configuration and Functions A0 1 16 VCC A1 2 3 15 14 Y0 A2 G0 4 13 G1 5 12 G2 Y7 6 7 8 GND A0 VCC 1 16 A1 2 15 Y0 Y2 Y3 A2 3 G0 4 14 13 Y1 Y2 11 Y4 G1 5 12 10 Y3 Y5 Y6 G2 6 11 Y4 Y7 7 10 Y5 9 Y1 Figure 5-1. D, DB, DGV, NS and PW Package 16-Pin (Top View) PAD 8 9 GND Y6 Figure 5-2. RGY and BQB Package 16-Pin (Top View) Table 5-1. Pin Functions PIN NAME NO. DESCRIPTION A0 1 I Address select 0 A1 2 I Address select 1 A2 3 I Address select 2 G2 6 I Strobe input G0 4 I Strobe input, active low G1 5 I Strobe input, active low GND 8 G Ground VCC 16 P Positive supply Y0 15 O Output 0 Y1 14 O Output 1 Y2 13 O Output 2 Y3 12 O Output 3 Y4 11 O Output 4 Y5 10 O Output 5 Y6 9 O Output 6 Y7 7 O Output 7 - Thermal Pad(2) Thermal Pad (1) (2) 4 TYPE(1) Signal Types: I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power BQB and RGY package only Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 7 V range(2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 VI Input voltage VO Voltage range applied to any output in the high-impedance or power-off state(2) range(2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage temperature range –65 V Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 5 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 6.3 Recommended Operating Conditions(1) SN74LV138A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High-level input voltage Low-level input voltage V 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V VCC = 2 V VIL UNIT 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V VCC × 0.3 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V –50 μA VCC = 2 V IOH VCC = 2.3 V to 2.7 V High-level output current –2 VCC = 3 V to 3.6 V –6 VCC = 4.5 V to 5.5 V VCC = 2 V IOL Δt/Δv Input transition rise or fall rate TA Operating free-air temperature 50 VCC = 2.3 V to 2.7 V Low-level output current μA 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V (1) mA –12 mA ns/V 20 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs. 6.4 Thermal Information SN74LV138A THERMAL METRIC(1) D DB DGV 73 82 120 NS PW RGY 108 39 BQB UNIT 86 °C/W 16 PINS RθJA (1) Junction-to-ambient thermal resistance 64 For more information about traditional and new thermal metrics, see IC Package Thermal Metrics. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH 6 High-Level Output Voltage TEST CONDITIONS VCC SN74LV138A MIN IOH = –50 μA 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –6 mA 3V 2.48 IOH = –12 mA 4.5 V 3.8 Submit Document Feedback TYP MAX UNIT VCC – 0.1 2 V Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN74LV138A VCC MIN TYP MAX IOL = 50 μA 2 V to 5.5 V 0.1 IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 4.5 V 0.55 VOL Low-Level Output Voltage II Input Current VI = 5.5 V or GND ICC Supply Current VI = VCC or GND, IO = 0 Ioff Input/Output Power-Off Leakage Current VI or VO = 0 to 5.5 V Ci Input Capacitance VI = VCC or GND IOL = 12 mA UNIT V 0 to 5.5 V ±1 μA 5.5 V 20 μA 0 5 μA 3.3 V 2.1 pF 6.6 Switching Characteristics, VCC = 2.5 V ± 0.25 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE Y CL = 15 pF TA = 25°C MIN A0, A1, A2 tpd SN74LV138A MAX MIN MAX 11.7 17.6 1 21 12.3 19.2 1 22 G0 or G1 11.4 18.2 1 21 A0, A1, A2 14.9 21.4 1 25 15.7 22.6 1 26 14.8 22 1 25 G2 tpd TYP G2 Y CL = 50 pF G0 or G1 UNIT ns ns 6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN A0, A1, A2 tpd G2 Y CL = 15 pF G0 or G1 A0, A1, A2 G2 tpd Y CL = 50 pF G0 or G1 SN74LV138A TYP MAX MIN MAX 8.1 11.4 1 13.5 8.4 12.8 1 15 7.8 11.4 1 13.5 10.3 15.8 1 18 10.6 16.3 1 18.5 10 14.9 1 17 UNIT ns ns 6.8 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE Y CL = 15 pF TA = 25°C MIN A0, A1, A2 tpd tpd G2 SN74LV138A TYP MAX MIN MAX 5.6 5.7 8.1 1 9.5 8.1 1 9.5 G0 or G1 5.4 8.1 1 9.5 A0, A1, A2 7 10.1 1 11.5 7.1 10.1 1 11.5 6.8 10.1 1 11.5 G2 Y CL = 50 pF G0 or G1 UNIT ns ns Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 7 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 6.9 Operating Characteristics TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, f = 10 MHz VCC TYP UNIT 3.3 V 16.8 5V 19.1 pF 6.10 Typical Characteristics 5.5 80 72 64 -40°C 125°C 25°C 5 4.5 4 48 VOH (V) ICC (nA) 56 40 32 3.5 3 2.5 24 16 2 8 1.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1 -16 5.5 2.5 V 3.3 V 5V -14 -12 -10 VCC (V) Figure 6-1. Supply Current (ICC) vs Supply Voltage (VCC) -8 IOH (mA) -6 -4 -2 0 Figure 6-2. Output Voltage vs Current in HIGH State 0.4 0.35 0.3 VOL (V) 0.25 0.2 0.15 0.1 2.5 V 3.3 V 5V 0.05 0 0 2 4 6 8 IOL (mA) 10 12 14 16 Figure 6-3. Output Voltage vs Current in LOW State 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 7 Parameter Measurement Information VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC VOH In-Phase Output 50% VCC 50% VCC VOL 50% VCC VOH 50% VCC VOL tPLZ ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH tPHL 50% VCC tPZL tPHL tPLH Out-of-Phase Output 0V VCC Output Control 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuits and Voltage Waveforms Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 9 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 8 Detailed Description 8.1 Overview The SN74LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCC operation. These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. 8.2 Functional Block Diagram 3:8 DECODER OUTPUT ENABLE 000 Y0 A0 001 Y1 A1 010 Y2 A2 011 Y3 G0 100 Y4 G1 101 Y5 G2 110 Y6 111 Y7 Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Standard CMOS Inputs This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in Implications of Slow or Floating CMOS Inputs. 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a 10-kΩ resistor, however, is recommended and will typically meet all requirements. 8.3.2 Balanced CMOS Push-Pull Outputs This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected. 8.3.3 Partial Power Down (Ioff) This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage current at each output is defined by the Ioff specification in the Electrical Characteristics table. 8.3.4 Clamp Diode Structure Figure 8-2 shows the inputs and outputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes Function Table ENABLE INPUTS(1) SELECT INPUTS OUTPUTS(2) G2 Y0 G0 G1 A2 A0 A1 Y1 Y20 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 11 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 Function Table (continued) ENABLE INPUTS(1) SELECT INPUTS OUTPUTS(2) G2 Y0 (1) (2) 12 G0 G1 A2 A0 A1 H L L L H H L L H H L L H H L L H H L L H Y1 Y20 Y3 H H H H L L L H H H L H H H H H L H H H H H H Y4 Y5 Y6 Y7 H H H H H L H H H H H L H H H H H H L H H H H H H L H = High Voltage Level, L = Low Voltage Level, X = Don’t Care H = Driving High, L = Driving Low, Z = High Impedance State Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LV138A is a low drive CMOS device that can be used for a multitude of output expansion applications where output ringing is a concern. The low-drive and slow-edge rates minimize overshoot and undershoot on the outputs. 9.2 Typical Application System Controller A2 G2 G1 G0 CONTROL LOGIC OUTPUT ENABLE A1 3:8 DECODER A0 Y0 Device 1 Y1 Device 2 Y2 Device 3 Y3 Device 4 Y4 Device 5 Y5 Device 6 Y6 Device 7 Y7 Device 8 Data Bus Figure 9-1. Output Exapnsion with Multiplexer 9.2.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74LV138A plus the maximum static supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74LV138A plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN74LV138A can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50 pF. The SN74LV138A can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 13 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. 9.2.2 Input Considerations Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74LV138A (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor value is often used due to these factors. The SN74LV138A has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. Refer to the Feature Description section for additional information regarding the inputs for this device. 9.2.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 9.2.4 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74LV138A to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. 9.2.5 Application Curves G2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Figure 9-2. Application Timing Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 15 SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 9.3 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for best results. 9.4 Layout 9.4.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 9.4.2 Layout Example GND VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 0.1 F A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 G0 4 13 Y2 G1 5 Unused input tied to GND 12 Y3 6 11 Y4 7 8 10 9 Y5 Y6 G2 Avoid 90° corners for signal lines Bypass capacitor placed close to the device Y7 GND Unused inputs tied to VCC Unused output left floating Figure 9-3. Layout Example for the SN74LV138A 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A SN74LV138A www.ti.com SCLS395N – APRIL 1998 – REVISED MARCH 2023 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation For related documentation, see the following: • • Texas Instruments, CMOS Power Consumption and Cpd Calculation application report Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application report 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: SN74LV138A 17 PACKAGE OPTION ADDENDUM www.ti.com 11-May-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV138ABQBR ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV138A Samples SN74LV138ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV138A Samples SN74LV138ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV138A Samples SN74LV138ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV138A Samples SN74LV138ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV138A Samples SN74LV138APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LV138A Samples SN74LV138APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV138A Samples SN74LV138ARGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LV138A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of