SN74LV161APWRE4


  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 9.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D D D D CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD SN54LV161A . . . FK PACKAGE (TOP VIEW) A B NC C D 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 ENP GND NC description/ordering information 4 The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation. QA QB NC QC QD LOAD ENT D 2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) CLK CLR NC VCC RCO D SN54LV161A . . . J OR W PACKAGE SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection ORDERING INFORMATION TOP-SIDE MARKING Tube of 40 SN74LV161AD Reel of 2500 SN74LV161ADR SOP − NS Reel of 2000 SN74LV161ANSR 74LV161A SSOP − DB Reel of 2000 SN74LV161ADBR LV161A Tube of 90 SN74LV161APW Reel of 2000 SN74LV161APWR Reel of 250 SN74LV161APWT TVSOP − DGV Reel of 2000 SN74LV161ADGVR LV161A CDIP − J Tube of 25 SNJ54LV161AJ SNJ54LV161AJ CFP − W Tube of 150 SNJ54LV161AW SNJ54LV161AW SOIC − D −40°C to 85°C TSSOP − PW −55°C 125°C −55 C to 125 C ORDERABLE PART NUMBER PACKAGE† TA LV161A LV161A LCCC − FK Tube of 55 SNJ54LV161AFK SNJ54LV161AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated 


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SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 description/ordering information (continued) These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS 2 CLR LOAD ENP OUTPUTS ENT CLK QA QB QC QD FUNCTION L X X X X L L L L Reset to “0” H L X X ↑ A B C D Preset Data H H X L ↑ No Change No Count H H L X ↑ No Change No Count H H H H ↑ Count up Count H X X X ↑ No Change No Count POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the overall logic diagram of the device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CK† TG CK† 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 recommended operating conditions (see Note 4) SN54LV161A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 Output voltage 0 0 VCC −50 V VCC × 0.3 5.5 0 VCC −50 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V V V µA −2 −6 −6 −12 −12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT 0.5 VCC × 0.3 VCC × 0.3 0 Input transition rise or fall rate MAX 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current SN74LV161A 0 200 0 200 0 100 0 100 0 20 0 20 mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV161A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 MIN TYP SN74LV161A MAX MIN VCC−0.1 2 VCC−0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOH = −6 mA IOH = −12 mA II ICC VCC TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.8 1.8 pF & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0  %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time before CLK↑ SN54LV161A MIN MAX SN74LV161A MIN CLK high or low 7 7 7 CLR low 7 7 7 CLR 4.5 4.5 4.5 Data (A, B, C, and D) 7.5 8.5 8.5 ENP, ENT 9.5 11 11 LOAD low 10 11.5 11.5 1.5 1.5 1.5 Hold time, all synchronous inputs after CLK↑ MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time before CLK↑ SN54LV161A MIN MAX SN74LV161A MIN CLK high or low 5 5 5 CLR low 5 5 5 CLR 2.5 2.5 2.5 Data (A, B, C, and D) 5.5 6.5 6.5 ENP, ENT 7.5 9 9 LOAD low 8 9.5 9.5 1 1 1 Hold time, all synchronous inputs after CLK↑ MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time before CLK↑ th Hold time, all synchronous inputs after CLK↑ MIN MAX SN74LV161A MIN CLK high or low 5 5 5 CLR low 5 5 5 CLR 1.5 1.5 1.5 Data (A, B, C, and D) 4.5 4.5 4.5 ENP, ENT 5 6 6 LOAD low 5 6 6 1 1 1 & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0  %$0# ( $$!# ## )(! .! $#, 8 SN54LV161A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd tPHL CLR CLK tpd tPHL SN74LV161A CL = 15 pF 50* 125* 40* 40 CL = 50 pF 30 95 25 25 MIN MAX MIN MAX 16.2* 1* 19.5* 1 19.5 RCO (count mode) 8.9* 17* 1* 20.5* 1 20.5 11.9* 20.6* 1* 24.5* 1 24.5 RCO 8.3* 15.7* 1* 19* 1 19 Q 8.8* 17* 1* 20.5* 1 20.5 RCO 9.8* 16.6* 1* 20* 1 20 Q 10.5 19.2 1 22.5 1 22.5 RCO (count mode) 11.7 20 1 23.5 1 23.5 14.5 23.6 1 27.5 1 27.5 11 18.7 1 22 1 22 CL = 15 pF CL = 50 pF RCO Q 11.4 20 1 23.5 1 23.5 RCO 12.6 19.6 1 23 1 23 CLR UNIT MHz 7.9* RCO (preset mode) ENT SN54LV161A MIN Q RCO (preset mode) ENT TA = 25°C TYP MAX LOAD CAPACITANCE ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0  %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX tpd* CL = 15 pF* 80* 165* 70* 70 CL = 50 pF 55 125 50 50 tPHL* CLR CLK tpd tPHL MIN MAX 15* 1 15 6.7 13.6 1* 16* 1 16 8.6 17.2 1* 20* 1 20 RCO 6.2 12.3 1* 14.5* 1 14.5 Q 6.5 13.6 1* 16* 1 16 RCO 7.2 13.2 1* 15.5* 1 15.5 Q 7.8 16.3 1 18.5 1 18.5 RCO (count mode) 8.7 17.1 1 19.5 1 19.5 10.6 20.7 1 23.5 1 23.5 RCO 8.3 15.8 1 18 1 18 Q 8.4 17.1 1 19.5 1 19.5 RCO 9.2 16.7 1 19 1 19 RCO (count mode) CL = 15 pF CL = 50 pF CLR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz 1* * On products compliant to MIL-PRF-38535, this parameter is not production tested. 10 MAX 12.8 RCO (preset mode) ENT MIN 6 RCO (preset mode) ENT SN74LV161A MIN Q CLK SN54LV161A LOAD CAPACITANCE ns ns 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLK tpd 220 115* 115 95 165 85 85 MIN MAX 9.5* 1 9.5 RCO (count mode) 5.1* 8.1* 1* 9.5* 1 9.5 6.3* 10.3* 1* 12* 1 12 RCO 4.8* 8.1* 1* 9.5* 1 9.5 Q 4.9* 9* 1* 10.5* 1 10.5 RCO 5.5* 8.6* 1* 10* 1 10 Q 5.9 10.1 1 11.5 1 11.5 RCO (count mode) 6.6 10.1 1 11.5 1 11.5 7.8 12.3 1 14 1 14 RCO 6.1 10.1 1 11.5 1 11.5 Q 6.3 11 1 12.5 1 12.5 RCO 6.9 10.6 1 12 1 12 ENT CL = 15 pF CL = 50 pF CLR UNIT MHz 1* RCO (preset mode) tPHL 135* CL = 50 pF MAX 8.1* CLR CLK SN74LV161A CL = 15 pF MIN 4.5* ENT tpd SN54LV161A MIN Q RCO (preset mode) tPHL TA = 25°C TYP MAX LOAD CAPACITANCE ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV161A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 0.8 V Quiet output, minimum dynamic VOL −0.2 −0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 25.8 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz 23.6 pF & & $'("%$ $#($ )(! $ # '("%1# ( #0$ )%# ' #1#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0  %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

  

  
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 50% VCC 0V tPZL Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC VCC Output Control tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV161AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV161A Samples SN74LV161APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples SN74LV161APWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of