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SN74LV164AD

SN74LV164AD

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC14_150MIL

  • 描述:

    IC 8-BIT SERIAL SHIFT REG 14SOIC

  • 数据手册
  • 价格&库存
SN74LV164AD 数据手册
SN74LV164A SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 SN74LV164A 8-Bit Parallel-Out Serial Shift Registers 1 Features 3 Description • • • The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V VCC operation. • • • • VCC operation of 2 V to 5.5 V Maximum tpd of 10.5 ns at 5 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (output VOH undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C Ioff supports live insertion, partial power-down mode, and back-drive protection Support mixed-mode voltage operation on all ports Latch-up performance exceeds 250 mA per JESD 17 2 Applications • • • • IP routers Enterprise switches Access control and security: access keypads and biometrics Smart meters: power line communication Package Information(1) PART NUMBER PACKAGE SN74LV164A (1) BODY SIZE (NOM) D (SOIC, 14) 8.65 mm × 3.91 mm DB (SSOP, 14) 6.20 mm × 5.30 mm DGV (TVSOP, 14) 3.60 mm × 4.40 mm NS (SOP, 14) 10.30 mm × 5.30 mm PW (TSSOP, 14) 5.00 mm × 4.40 mm RGY (VQFN, 14) 3.50 mm × 3.50 mm BQA (WQFN, 14) 3.00 mm × 2.50 mm For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings(1) .................................... 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Timing Requirements: VCC = 2.5 V ± 0.2 V.................6 6.7 Timing Requirements: VCC = 3.3 V ± 0.3 V.................6 6.8 Timing Requirements: VCC = 5 V ± 0.5 V....................7 6.9 Switching Characteristics: VCC = 2.5 V ± 0.2 V...........7 6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V.........7 6.11 Switching Characteristics: VCC = 5 V ± 0.5 V............ 8 6.12 Noise Characteristics(1) ............................................8 6.13 Operating Characteristics......................................... 8 6.14 Typical Characteristics.............................................. 9 7 Parameter Measurement Information.......................... 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 10 Power Supply Recommendations..............................14 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................16 12.1 Receiving Notification of Documentation Updates..16 12.2 Support Resources................................................. 16 12.3 Trademarks............................................................. 16 12.4 Electrostatic Discharge Caution..............................16 12.5 Glossary..................................................................16 13 Mechanical, Packaging, and Orderable Information.................................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (February 2015) to Revision J (December 2022) Page • Updated the format of tables, figures, and cross-references throughout the document.....................................1 Changes from Revision H (April 2005) to Revision I (February 2015) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 5 Pin Configuration and Functions A VCC 1 14 B 2 13 QH QA 3 12 QG QB 4 11 QF QC 5 10 QE QD 6 9 CLR PAD 7 8 GND CLK Figure 5-2. RGY or BQA Package 14-PIN VQFN or WQFN Top View Figure 5-1. D, DB, DGV, NS, or PW Package 14-PIN SOIC, SSOP, TVSOP, SOP, or TSSOP Top View Table 5-1. Pin Functions PIN NO. NAME TYPE(1) DESCRIPTION 1 A I Serial input A 2 B I Serial input B 3 QA O Output A 4 QB O Output B 5 QC O Output C 6 QD O Output D 7 GND — Ground pin 8 CLK I Storage clock 9 CLR I Storage clear 10 QE O Output E 11 QF O Output F 12 QG O Output G 13 QH O Output H 11 QH' O QH inverted 14 VCC — Power pin - PAD — Thermal Pad(2) (1) (2) I = input, O = output RGY and BQA packages only Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 3 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings(1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage –0.5 7 V voltage(2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 VI Input VO Voltage applied to any output in the high-impedance or power-off state(2) voltage(2) (3) UNIT VO Output IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) (3) Storage temperature –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) 4 Electrostatic discharge JS-001(1) Charged-device model (CDM), per JEDEC specification JESD22C101(2) UNIT ±2000 ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions over recommended operating free-air temperature range (unless otherwise noted)(1) SN74LV164A VCC MIN MAX 2 5.5 Supply voltage VCC = 2 V VIH High-level input voltage Low-level input voltage VI Input voltage VO Output voltage VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC = 4.5 V to 5.5 V High-level output current VCC × 0.3 5.5 0 VCC V –50 µA VCC = 2.3 V to 2.7 V –2 VCC = 3 V to 3.6 V –6 VCC = 4.5 V to 5.5 V Low-level output current Δt/Δv Input transition rise or fall rate (1) mA 50 VCC = 2.3 V to 2.7 V 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA V –12 VCC = 2 V IOL V 0 VCC = 2 V IOH V 1.5 VCC = 2.3 V to 2.7 V VCC = 2 V VIL UNIT µA mA ns/V 20 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6.4 Thermal Information SN74LV164A THERMAL METRIC(1) D (SOIC) DB (SSOP) DGV (TVSOP) NS (SOP) PW (TSSOP) RGY (VQFN) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 92.6 104.4 126.7 89.3 120.2 54.5 RθJC(top) Junction-to-case (top) thermal resistance 53.9 57 50 46.9 48.9 67 RθJB Junction-to-board thermal resistance 46.8 51.7 59.6 48 61.9 30.5 ψJT Junction-to-top characterization parameter 18.9 18.6 5.8 13.7 5.7 2.3 ψJB Junction-to-board characterization parameter 46.6 51.2 58.9 47.7 61.3 30.5 RθJC(bot) Junction-to-case (bottom) thermal resistance – – – – – 11.2 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 5 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMTER TEST CONDITIONS SN74LV164A –40°C to 85°C VCC MIN TYP SN74LV164A –40°C to 125°C MAX MIN TYP UNIT MAX IOH = –50 µA 2 V to 5.5 V IOH = –2 mA 2.3 V 2 2 IOH = –6 mA 3V 2.48 2.48 IOH = –12 mA 4.5 V 3.8 3.8 IOL = 50 µA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 IOL = 12 mA 4.5 V 0.55 0.55 II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 µA ICC VI = VCC or GND, 5.5 20 20 µA Ioff VI or VO = 0 to 5.5 V 5 µA Ci VI = VCC or GND VOH VOL IO = 0 VCC – 0.1 VCC – 0.1 V 0.1 0 0.1 5 3.3 V 2.2 2.2 V pF 6.6 Timing Requirements: VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) SN74LV164A –40°C to 85°C TA = 25°C MIN tw Pulse duration tsu Setup time th Hold time CLR low MAX MIN SN74LV164A –40°C to 125°C MAX MIN 6 6.5 6.5 CLK high or low 6.5 7.5 7.5 Data before CLK↑ 6.5 8.5 8.5 3 3 3 –0.5 0 0 CLR inactive Data after CLK↑ UNIT MAX ns ns ns 6.7 Timing Requirements: VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) SN74LV164A –40°C to 85°C TA = 25°C MIN 6 tw Pulse duration tsu Setup time th Hold time MAX MIN SN74LV164A –40°C to 125°C MAX MIN CLR low 5 5 5 CLK high or low 5 5 5 Data before CLK↑ CLR inactive Data after CLK↑ 5 6 6 2.5 2.5 2.5 0 0 0 Submit Document Feedback UNIT MAX ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 6.8 Timing Requirements: VCC = 5 V ± 0.5 V over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) SN74LV164A –40°C to 85°C TA = 25°C MIN tw Pulse duration tsu Setup time th Hold time MAX MIN SN74LV164A –40°C to 125°C MAX CLR low 5 5 5 CLK high or low 5 5 5 Data before CLK↑ 4.5 4.5 4.5 CLR inactive 2.5 2.5 2.5 1 1 1 Data after CLK↑ UNIT MIN MAX ns ns ns 6.9 Switching Characteristics: VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK tPHL Q CLR Q tpd CLK Q tPHL CLR Q (1) LOAD CAPACITANCE SN74LV164A –40°C to 85°C TA = 25°C MIN TYP CL = 15 pF 55(1) 105(1) 50 50 CL = 50 pF 45 85 40 40 CL = 15 pF CL = 50 pF MAX MIN SN74LV164A –40°C to 125°C MAX MIN UNIT MAX MHz 9.2(1) 17.6(1) 1 20 1 21 8.6(1) 16(1) 1 18 1 18.5 11.5 21.1 1 24 1 25 10.8 19.5 1 22 1 22.5 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 6.10 Switching Characteristics: VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd tPHL CLK Q CLR Q tpd CLK Q tPHL CLR Q (1) LOAD CAPACITANCE SN74LV164A –40°C to 85°C TA = 25°C MIN TYP CL = 15 pF 80(1) 155(1) 65 65 CL = 50 pF 50 120 45 45 CL = 15 pF CL = 50 pF MAX MIN SN74LV164A –40°C to 125°C MAX MIN UNIT MAX MHz 6.4(1) 12.8(1) 1 15 1 16 6(1) 12.8(1) 1 15 1 16 8.3 16.3 1 18.5 1 19.5 7.9 16.3 1 18.5 1 19.5 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 7 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 6.11 Switching Characteristics: VCC = 5 V ± 0.5 V over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLK tPHL Q CLR Q tpd CLK Q tPHL CLR Q (1) LOAD CAPACITANCE SN74LV164A –40°C to 85°C TA = 25°C MIN TYP CL = 15 pF 125(1) 220(1) 105 95 CL = 50 pF 85 165 75 65 CL = 15 pF CL = 50 pF MAX MIN SN74LV164A –40°C to 125°C MAX MIN UNIT MAX MHz 4.5(1) 9(1) 1 10.5 1 11.5 4.2(1) 8.6(1) 1 10 1 11 6 11 1 12.5 1 13 5.8 10.6 1 12.5 1 13 ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. 6.12 Noise Characteristics(1) VCC = 3.3 V, CL = 50 pF, TA = 25°C SN74LV164A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.28 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.22 –0.8 V VOH(V) Quiet output, minimum dynamic VOH 3.09 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) V 2.31 V 0.99 V UNIT Characteristics are for surface-mount packages only. 6.13 Operating Characteristics TA = 25°C PARAMETER Cpd 8 Power dissipation capacitance TEST CONDITIONS CL = 50 pF Submit Document Feedback f = 10 MHz VCC TYP 3.3 V 48.1 5V 47.5 pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 Figure 6-1. Typical Clear, Shift, and Clear Sequences 6.14 Typical Characteristics Figure 6-2. TPD vs. Temperature at 3.3 V Figure 6-3. TPD vs. VCC at 25°C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 9 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 7 Parameter Measurement Information Figure 7-1. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The SNx4LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation. These devices feature NAND-gated serial (A and B) inputs and an asynchronous clear ( CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. 8.2 Functional Block Diagram Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description The wide operating range allows the device to be used in a variety of systems that use different logic levels. The low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce stabilizes the performance of non-switching outputs while another output is switching. 8.4 Device Functional Modes Table 8-1. Function Table(1)(2) INPUTS OUTPUTS CLR CLK A B QA QB L X X X L L H L X X QA0 QB0 QH0 H ↑ H H H QAn QGn H ↑ L X L QAn QGn H ↑ X L L QAn QGn (1) (2) ... QH L QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = the level of QA or QG before the most recent ↑ transition of the clock: indicates a 1-bit shift. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 11 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LV164A is a low drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low-drive and slow-edge rates will minimize overshoot and undershoot on the outputs. 9.2 Typical Application Figure 9-1. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure • • 12 Recommended input conditions: – Rise time and fall time specs. See (Δt/ΔV) in Section 6.3. – Specified high and low level. See (VIH and VIL) in Section 6.3. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. Recommended output conditions: – Load currents should not exceed 25 mA per output and 50 mA total for the part. – Outputs should not be pulled above VCC. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 9.2.3 Application Curves Figure 9-2. Switching Characteristics Comparison Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 13 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Section 6.3. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal for best results. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float when disabled. 11.2 Layout Example Figure 11-1. Layout Example Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A 15 SN74LV164A www.ti.com SCLS403J – APRIL 1998 – REVISED DECEMBER 2022 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV164A PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV164AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164ADGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164ANSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV164A Samples SN74LV164APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV164A Samples SN74LV164ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LV164A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
SN74LV164AD 价格&库存

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