SN74LV166APWTE4


       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D D D Direct Overriding Clear D Parallel-to-Serial Conversion D Latch-Up Performance Exceeds 100 mA Per 2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down-Mode Operation Synchronous Load D JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54LV166A . . . J OR W PACKAGE SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 A SER NC VCC SH/LD 1 VCC SH/LD H QH G F E CLR B C NC D CLK INH 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 H QH NC G F CLK GND NC CLR E SER A B C D CLK INH CLK GND SN54LV166A . . . FK PACKAGE (TOP VIEW) NC − No internal connection description/ordering information The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION TOP-SIDE MARKING Tube of 40 SN74LV166AD Reel of 2500 SN74LV166ADR SOP − NS Reel of 2000 SN74LV166ANSR 74LV166A SSOP − DB Reel of 2000 SN74LV166ADBR LV166A Tube of 90 SN74LV166APW Reel of 2000 SN74LV166APWR Reel of 250 SN74LV166APWT TVSOP − DGV Reel of 2000 SN74LV166ADGVR LV166A CDIP − J Tube of 25 SNJ54LV166AJ SNJ54LV166AJ CFP − W Tube of 150 SNJ54LV166AW SNJ54LV166AW LCCC − FK Tube of 55 SNJ54LV166AFK SOIC − D −40°C to 85°C TSSOP − PW −55°C 125°C −55 C to 125 C ORDERABLE PART NUMBER PACKAGE† TA LV166A LV166A SNJ54LV166AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated 


   !"#$%& "!&'& (   &)!*$'!& "#**%& ' !) +#,-"'!& '%. *!#" "!&)!*$ ! +%")"'!& +%* % %*$ !) %/' &*#$%& '&'* 0'**'&1. *!#"!& +*!"%&2 !% &! &%"%'*-1 &"-#% %&2 !) '-+'*'$%%*. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 description/ordering information (continued) The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE OUTPUTS INPUTS 2 INTERNAL QH CLR SH/LD CLK INH CLK SER PARALLEL A...H QA QB L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L ↑ X a...h a b h H H L ↑ H X H QAn QGn H H L ↑ L X L QAn QGn H X H ↑ X X QA0 QB0 QH0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 logic diagram (positive logic) A SH/LD SER B 2 15 C D 3 4 1D C1 R 1D C1 R E F G H 5 10 11 12 14 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1 CLK INH CLK CLR 1D C1 R 6 7 9 13 QH Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. typical clear, shift, load, inhibit, and shift sequence CLK CLK INH CLR SER SH/LD Parallel Inputs A H B L C H D L E H F L G H H H QH Serial Shift Clear H Inhibit H L H L H L H Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . −0.5 V to VCC + 0.5 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 recommended operating conditions (see Note 4) SN54LV166A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 Output voltage UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 0 0 VCC −50 VCC = 2 V VCC = 2.3 V to 2.7 V V VCC −50 µA 0 V −2 −6 −6 −12 −12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 200 200 100 100 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V V VCC × 0.3 5.5 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate MAX 1.5 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current MIN 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current SN74LV166A mA µA mA ns/V VCC = 4.5 V to 5.5 V 20 20 TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV166A PARAMETER VOH VOL TEST CONDITIONS IOH = −50 µA IOH = −2 mA IOL = 6 mA IOL = 12 mA Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 TYP SN74LV166A MAX MIN VCC−0.1 2 VCC−0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOL = 50 µA IOL = 2 mA VI = 5.5 V or GND VI = VCC or GND, MIN 2 V to 5.5 V IOH = −6 mA IOH = −12 mA II ICC VCC TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.6 1.6 pF (  &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !* %2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%* +%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 ! "'&2% !* "!&&#% %% +*!#" 0!# &!"%. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX CLR low tw Pulse duration CLK high or low CLK INH before CLK↑ Data before CLK↑ tsu Setup time SH/LD before CLK↑ SER before CLK↑ CLR↑ inactive before CLK↑ th Hold time Data after CLK↑ SN54LV166A MIN MAX SN74LV166A MIN 8 9 9 8.5 9 9 7 7 7 6.5 8.5 8.5 7 8.5 8.5 8.5 9.5 9.5 6 7 7 −0.5 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu th Pulse duration Setup time Hold time SN54LV166A MIN MAX SN74LV166A MIN CLR low 6 7 7 CLK high or low 6 7 7 CLK INH before CLK↑ 5 5 5 Data before CLK↑ 5 6 6 SH/LD before CLK↑ 5 6 6 SER before CLK↑ 5 6 6 CLR↑ inactive before CLK↑ 4 4 4 Data after CLK↑ 0 0 0 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time Hold time MAX MIN4 CLR low 5 5 5 4 4 4 CLK INH before CLK↑ 3.5 3.5 3.5 Data before CLK↑ 4.5 4.5 4.5 SH/LD before CLK↑ 4 4 4 SER before CLK↑ 4 4 4 3.5 3.5 3.5 1 1 1 Data after CLK↑ (  &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !* %2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%* +%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 ! "'&2% !* "!&&#% %% +*!#" 0!# &!"%. 6 MIN SN74LV166A CLK high or low CLR↑ inactive before CLK↑ th SN54LV166A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL TA = 25°C TYP MAX CLK tPHL CLR tpd CLK temperature SN54LV166A MIN CL = 15 pF 50* 105* 45* 45 CL = 50 pF 40 80 35 35 QH CL = 15 pF QH CL = 50 pF MIN MAX range, SN74LV166A LOAD CAPACITANCE CLR tpd free-air MIN MAX UNIT MHz 8.8* 16* 1* 18* 1 18 9.2* 19.8* 1* 22* 1 22 11.3 19.5 1 22 1 22 11.8 23.3 1 26 1 26 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL CLR tpd CLK tPHL CLR tpd CLK free-air TA = 25°C TYP MAX temperature SN54LV166A SN74LV166A LOAD CAPACITANCE MIN CL = 15 pF 65* 150* 55* 55 CL = 50 pF 60 120 50 50 QH CL = 15 pF QH CL = 50 pF MIN MAX range, MIN MAX UNIT MHz 6.3* 12.5* 1* 15* 1 15 6.6* 15.4* 1* 18* 1 18 7.9 16.3 1 18.5 1 18.5 8.3 18.9 1 21.5 1 21.5 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL CLR tpd CLK tPHL CLR tpd CLK LOAD CAPACITANCE free-air TA = 25°C MIN TYP MAX temperature SN54LV166A MIN MAX SN74LV166A MIN CL = 15 pF 110* 205* 90* 90 CL = 50 pF 95 160 85 85 QH CL = 15 pF QH CL = 50 pF range, MAX UNIT MHz 4.6* 8.6* 1* 10* 1 10 4.8* 9.9* 1* 11.5* 1 11.5 5.7 10.6 1 12 1 12 6.1 11.9 1 13.5 1 13.5 VCC 3.3 V TYP 5V 44.5 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz UNIT 39.1 pF (  &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !* %2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%* +%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 ! "'&2% !* "!&&#% %% +*!#" 0!# &!"%. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

       
 

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 50% VCC 0V tPZL Output Waveform 1 S1 at VCC (see Note B) tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV166AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV166A Samples SN74LV166APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples SN74LV166APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV166A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of