SN74LV174A
SCLS401H – APRIL 1998 – REVISED DECEMBER 2022
SN74LV174A Hex D-Type Flip-Flops With Clear
1 Features
3 Description
•
•
•
The 'LV174A devices are hex D-type flip-flops
designed for 2 V to 5.5 V VCC operation.
•
•
•
VCC operation of 2 V to 5.5 V
Maximum tpd of 8.5 ns at 5 V
Typical VOLP (output ground bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250 mA per JESD
17
2 Applications
•
•
•
Output expansion
LED matrix control
7-segment display control
Package Information(1)
PART NUMBER
SN74LV174A
(1)
PACKAGE
BODY SIZE (NOM)
DGV (TVSOP, 16)
4.00 mm × 3.50 mm
PW (TSSOP, 16)
5.00 mm × 4.40 mm
NS (SO ,16)
10.20 mm × 5.30 mm
D (SOIC, 16)
9.00 mm × 3.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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SCLS401H – APRIL 1998 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
5.1 Specifications..............................................................3
6 Parameter Measurement Information.......................... 10
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................13
8 Application and Implementation.................................. 14
8.1 Application Information............................................. 14
8.2 Typical Application.................................................... 14
9 Power Supply Recommendations................................14
10 Layout...........................................................................15
10.1 Layout Guidelines................................................... 15
11 Device and Documentation Support..........................16
11.1 Documentation Support.......................................... 16
11.2 Receiving Notification of Documentation Updates.. 16
11.3 Support Resources................................................. 16
11.4 Trademarks............................................................. 16
11.5 Electrostatic Discharge Caution.............................. 16
11.6 Glossary.................................................................. 16
12 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2005) to Revision H (December 2022)
Page
• Updated the format for tables, figures, and cross-references throughout the document....................................1
2
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5 Pin Configuration and Functions
Figure 5-1. D, DW, or PW Package,
16-Pin SOIC, SOP or TSSOP
(Top View)
Figure 5-2. BQB or RGY Package,
16-Pin WQFN or VQFN
(Transparent Top View)
Table 5-1. Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
CLR
1
I
Clear Pin
1Q
2
O
Q Output
1D
3
I
Q Output
2D
4
I
Q Output
2Q
5
O
Q Output
3D
6
I
Q Output
3Q
7
O
Q Output
GND
8
—
Ground Pin
CLK
9
I
Clock Pin
4Q
10
O
Q Output
4D
11
I
Q Output
5Q
12
O
Q Output
5D
13
I
Q Output
6D
14
I
Q Output
6Q
15
O
Q Output
VCC
16
P
Power Pin
5.1 Specifications
5.1.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage range
VCC
–0.5
7
V
Input voltage range(2)
VI
–0.5
7
V
Voltage range applied to any output
in the
VO
high-impedance or power-off state(2)
–0.5
7
V
Output voltage range applied in the
high or low state(2) (3)
VO
–0.5 VCC + 0.5
V
Input clamp current
IIK
VI < 0
–20
mA
Output clamp current
IOK
VO < 0
–50
mA
Continuous output current
IO
VO = 0 to VCC
±25
mA
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over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
±50
mA
Continuous current through VCC or
GND
Junction temperature
TJ
−55
150 °C
Storage temperature range
Tstg
−65
150
(1)
(2)
(3)
°CW
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output damp current ratings are observed.
This value is limited to 5.5 V maximum.
5.1.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
±2000
Machine Model (MM), per JEDEC specification
±200
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002
(1)
(2)
4
UNIT
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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5.1.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
High or low state
5.5
V
0
VCC
V
–50
µA
VCC = 2.3 V to 2.7 V
High-level output current
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
50
VCC = 2.3 V to 2.7 V
Low-level output current
µA
2
VCC = 3 V to 3.6 V
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
(1)
mA
–12
VCC = 2 V
IOL
V
0
VCC = 2 V
IOH
V
1.5
VCC = 2.3 V to 2.7 V
VCC = 2 V
VIL
UNIT
mA
ns/V
20
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
5.1.4 Thermal Information
SN74LV174A
THERMAL
METRIC(1)
D
DB
DGV
NS
PW
UNIT
64
108
°C/W
16 PINS
RθJA
(1)
Junction-to-ambient thermal
resistance
73
82
120
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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5.1.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
2 V to 5.5 V
IOH = –2 mA
2.3 V
IOH = –6 mA
VOH
MIN
TYP
V
2
2.48
3.8
0.1
0.4
4.5 V
0.44
IOL = 50 µA
2 V to 5.5 V
0.1
IOL = 2 mA
2.3 V
0.4
IOL = 6 mA
3V
0.44
4.5
0.55
IOL = 12 mA
II
VI = 5.5 V or GND
ICC
VI = V CCor GND,
Ioff
VI or V O = 0 to 5.5 V
Ci
VI = VCC or GND
IO = 0
UNIT
MAX
VCC – 0.1
3V
IOH = –12 mA
VOL
SN74LV174A
VCC
V
0 V to 5.5 V
±1
µA
5.5 V
20
µA
0V
5
µA
3.3 V
1.7
pF
5.1.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
6
tw
Pulse duration
tsu
Setup time before
CLK↑
th
Hold time data after
CLK↑
SN74LV174A
MAX
MIN
CLR low
6
6.5
CLK high or low
7
7
8.5
9.5
4
4
− 0.5
0
Data
CLR inactive
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MAX
UNIT
ns
ns
ns
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5.1.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before
CLK↑
th
Hold time data after
CLK↑
SN74LV174A
MAX
MIN
CLR low
5
5
CLK high or low
5
5
Data
5
6
CLR inactive
3
3
0
0
UNIT
MAX
ns
ns
ns
5.1.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before
CLK↑
th
Hold time data after
CLK↑
CLR low
CLK high or low
5
SN74LV174A
MAX
MIN
UNIT
MAX
5
ns
5
5
ns
Data
4.5
4.5
ns
CLR inactive
2.5
2.5
0.5
0.5
ns
ns
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5.1.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
CLR
tpd
Q
CLK
CLR
tpd
SN74LV174A
TYP
CL = 15 pF
55
115
50
CL = 50pF
45
90
40
CL = 50 pF
MAX
MIN
MAX
17.3
1
19.5
8.4
17.1
1
19
8.2
21.9
1
23.5
10.8
20.6
1
23
tsk(o)
UNIT
MHz
6.3
CL = 15pF
Q
CLK
TA = 25°C
MIN
2
ns
ns
2
5.1.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
CLR
tpd
Q
CLK
CLR
tpd
SN74LV174A
TYP
CL = 15 pF
95
170
80
CL = 50 pF
55
130
50
CL = 15 pF
Q
CLK
TA = 25°C
MIN
CL = 50 pF
MAX
MIN
MAX
MHz
4.5
11.4
1
13.5
5.8
11
1
13
6
14.9
1
17
7.5
14.5
1
16.5
tsk(o)
UNIT
1.5
ns
ns
1.5
5.1.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
CL = 15 pF
130
CL = 50 pF
90
fmax
tpd
tpd
CLR
Q
CLK
CLR
CL = 15 pF
Q
CLK
TA = 25°C
LOAD
CAPACITANCE
CL = 50 pF
tsk(o)
SN74LV174A
MAX
MIN
MAX
240
110
5
180
80
3
7.6
1
9
4.1
7.2
1
8.5
4.2
9.6
1
11
5.5
9.2
1
10.5
1
UNIT
MHz
ns
ns
1
5.1.12 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C(1)
PARAMETER
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.34
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
8
SN74LV174A
MIN
3.02
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
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5.1.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
14
5V
15.1
UNIT
pF
5.1.14 Typical Characteristics
13
CL=50pF
12
tPD (ns)
11
10
9
8
7
6
2.5
3
3.5
4
VCC (V)
4.5
5
C001
Figure 5-3. TPD vs VCC
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6 Parameter Measurement Information
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
0V
tPHL
50% VCC
tPHL
Out-of-Phase
Output
50% VCC
VOL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
A.
B.
C.
D.
E.
F.
G.
H.
50% VCC
0V
tPLZ
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPZL
VOH
In-Phase
Output
VCC
Output
Control
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
The outputs are measured one at a time, with one input transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPHL and tPLH are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 6-1. Load Circuit and Voltage Waveforms
10
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7 Detailed Description
7.1 Overview
The 'LV174A devices are positive-edge-triggered flip-flops with a direct clear (CLR) input. Information at the data
(D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or low level, the
D-input signal has no effect at the output.
7.2 Functional Block Diagram
Figure 7-1. Logic Diagram (Positive Logic)
Figure 7-2.
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7.3 Feature Description
7.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10-kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
7.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
7.3.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
7.3.4 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
7.3.5 Clamp Diode Structure
Figure 7-3 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
12
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Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 7-3. Electrical Placement of Clamping Diodes for Each Input and Output
7.4 Device Functional Modes
Table 7-1. Function Table
INPUTS(1)
(1)
OUTPUT
CLR
CLK
D
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Qo
H = High Voltage Level, L = Low Voltage Level, X = Do not Care, Z = High Impedance
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The SN74LV174A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs are 5-V tolerant allowing for down translation to VCC.
8.2 Typical Application
8.2.1 Application Curves
SER
QA
QB
QC
QC
QD
QE
QF
Output Registers
QB
Serial Registers
Output Registers
QA
Serial Registers
SER
QD
QE
QF
QG
QG
QH
QH
QH¶
QH¶
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
Figure 8-1. Simplified Functional Diagram Showing Clock Operation
9 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in Section 5.1.3.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
14
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10 Layout
10.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because
the undefined voltages at the outside connections result in undefined operational states. All unused inputs of
digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage
specifications, to prevent them from floating. The logic level that must be applied to any particular unused input
depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more
sense for the logic function or is more convenient.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV174A
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV174AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV174A
Samples
SN74LV174ADGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV174A
Samples
SN74LV174ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV174A
Samples
SN74LV174ANSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV174A
Samples
SN74LV174APW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV174A
Samples
SN74LV174APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV174A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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