SN74LV175APWG4

SN74LV175A SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 SN74LV175A Quadruple D-Type Flip-Flops With Clear 1 Features • • • • • • • 3 Description VCC operation of 2 V to 5.5 Maximum tpd of 7.5 ns at 5 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (output VOH undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C Ioff supports partial-power-down mode operation Supports mixed-mode voltage operation on all ports Contains four flip-flops with double-rail outputs The SN74LV175A device is quadruple D-type flipflops designed for 2 V to 5.5 V VCC operation. These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop. Package Information DEVICE NUMBER SN74LV175A 2 Applications • • • PACKAGE BODY SIZE (NOM) SOIC (16) 9.9 mm × 3.9 mm SOP (16) 10.3 mm × 1.95 mm TSSOP (16) 5 mm × 4.4 mm TVSOP (16) 3.6 mm × 4.4 mm Buffer or storage registers Shift registers Pattern generators Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configurations and Functions.................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................6 6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................6 6.8 Timing Requirements, VCC = 5 V ± 0.5 V....................7 6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........7 6.10 Switching Characteristics, VCC = 3.5 V ± 0.3 V ...... 7 6.11 Timing Requirements, VCC = 5 V ± 0.5 V.................. 8 6.12 Noise Characteristics................................................ 8 6.13 Operating Characteristics......................................... 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................11 8.4 Device Functional Modes..........................................11 9 Application and Implementation.................................. 12 9.1 Application Information............................................. 12 10 Power Supply Recommendations..............................12 11 Layout........................................................................... 13 11.1 Layout Guidelines................................................... 13 12 Receiving Notification of Documentation Updates.. 13 13 Trademarks.................................................................. 14 14 Glossary....................................................................... 14 15 Mechanical, Packaging, and Orderable Information.................................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (April 2005) to Revision H (December 2022) Page • Updated the format for tables, figures, and cross-references throughout the document....................................1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 5 Pin Configurations and Functions Figure 5-1. D, DGV, NS, or PW Package (Top View) Table 5-1. Pin Functions PIN NO. NAME 1 1 OE 2 3 4 5 6 7 TYPE DESCRIPTION I Output Enable 1 1A1 I 1A1 Input 1Y1 O 1Y1 Output 1A2 I 1A2 Input 1Y2 O 1Y2 Output 1A3 I 1A3 Input 1Y3 O 1Y3 Output 8 GND — Ground Pin 9 1Y4 O 1Y4 Output 10 1A4 I 1A4 Input 11 2Y1 O 2Y1 Output 12 2A1 I 2A1 Input 13 2Y2 O 2Y2 Output 14 2A2 I 2A2 Input 15 2 OE I Output Enable 2 16 VCC — Power Pin Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 3 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state –0.5 7 V VO Output voltage range –0.5 VCC + 0.5 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA 150 °C Continuous current through VCC or GND Tstg Storage temperature range –65 V 6.2 ESD Ratings VALUE Human-Body Model (A114-A) V(ESD) 4 Electrostatic discharge Machine Model (A115-A) 200 Charged-Device Model (C101) 1000 Submit Document Feedback UNIT 2000 V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted MIN VCC MAX Supply voltage 2 VCC = 2 V VIH High-level input voltage UNIT 5.5 V 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 V VCC = 2 V 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V –50 µA VCC = 4.5 V to 5.5 V VCC × 0.3 VCC = 2 V IOH VCC = 2.3 V to 2.7 V High-level output current –2 VCC = 3 V to 3.6 V –6 VCC = 4.5 V to 5.5 V 50 VCC = 2.3 V to 2.7 V Low-level output current Input transition rise or fall rate TA Operating free-air temperature µA 2 VCC = 3 V to 3.6 V Δt/Δv mA –12 VCC = 2 V IOL V 6 VCC = 4.5 V to 5.5 V 12 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V mA ns/V 20 –40 85 °C 6.4 Thermal Information D THERMAL METRIC RθJA DB DGV NS PW 64 108 UNIT 20 PINS Junction-to-ambient thermal resistance 73 82 20 °C/W 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC MIN TYP IOH = –50 µA 2 V to 5.5 V VCC – 0.1 IOH = –2 mA 2.3 V 2 IOH = –6 mA 3V 2.48 IOH = –12 mA 4.5 V 3.8 IOL = 50 µA 2 V to 5.5 V MAX V 0.1 IOL = 2 mA 2.3 V 0.4 IOL = 6 mA 3V 0.44 IOL = 12 mA 4.5 V 0.55 II VI = 5.5 V or GND 0 to 5.5 V ±1 ICC VI = VCC or GND, 5.5 V 20 VOL IO = 0 UNIT V µA µA Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 5 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND VCC MIN TYP MAX 0V UNIT 5 3.3 V 1.4 µA pF 6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) (see #unique_15/ unique_15_Connect_42_GUID-C2E075CB-50B1-499D-A291-881D29344407referenceTitle) TA = 25°C MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ CLR low SN74LV175A MAX MIN 6 6 6.5 7 Data 7 7.5 CLR inactive 7 7.5 0.5 1 CLK high or low MAX UNIT ns ns ns 6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C MIN 6 tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN74LV175A MAX MIN CLR low 5 5 CLK high or low 5 5 Data 5 5 CLR inactive 5 5 1 1 Submit Document Feedback MAX UNIT ns ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 6.8 Timing Requirements, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN74LV175A MAX MIN CLR low 5 5 CLK high or low 5 5 Data 4 4 CLR inactive 5 5 1 1 UNIT MAX ns ns ns 6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd CLR Any tpd CLK Any tsk(o) CLR Any tPHL CLK Any LOAD CAPACITANCE TA = 25°C SN74LV175A MIN TYP CL = 15 pF 50 105 45 CL = 50 pF 40 80 35 CL = 15 pF MAX MIN 7.9 16.6 1 MAX UNIT MHz 20 ns 9.3 18.8 1 22 ns 10.4 21.6 1 25.5 ns 12 23.3 1 27 ns 2 ns CL = 50 pF tsk(o) 2 over operating free-air temperature range (unless otherwise noted) 6.10 Switching Characteristics, VCC = 3.5 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLR tpd CLK CLR CLK LOAD CAPACITANCE SN74LV175A TYP CL = 15 pF 90 155 75 CL = 50 pF 50 120 45 Any CL = 15 pF Any CL = 50 pF tsk(o) TA = 25°C MIN CL = 50 pF MAX MIN MAX MHz 5.5 10.1 1 12 6.5 11.5 1 13.5 7.4 13.6 1 15.5 8.4 15 1 17 1.5 UNIT 1.5 nsns nsns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 7 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 6.11 Timing Requirements, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) CLK tpd CLR CLK SN74LV175A MIN TYP CL = 15 pF 150 215 125 CL = 50 pF 85 165 75 fmax CLR TA = 25°C LOAD CAPACITANCE Any CL = 15 pF Any CL = 50 pF tsk(o) MAX MIN MAX MHz 3.7 6.4 1 7.5 4.6 7.3 1 8.5 5.3 8.4 1 9.5 6 9.3 1 10.5 CL = 50 pF UNIT 1 1 nsns nsns ns 6.12 Noise Characteristics VCC = 3.3 V, CL = 50 pF, TA = 25°C PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.3 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 3 V 2.31 V 0.99 V 6.13 Operating Characteristics TA = 25°C PARAMETER Cpd 8 Power dissipation capacitance TEST CONDITIONS CL = 50 pF f = 10 MHz Submit Document Feedback VCC TYP 3.3 V 13.6 5V 14.5 UNIT pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 7 Parameter Measurement Information A. B. C. D. E. F. G. H. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. The outputs are measured one at a time, with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPHL and tPLH are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 9 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The SN74LV175A device is an octal D-type flip-flop designed for 2-V to 5.5-V VCC operation. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. This device is a positive-edge-triggered flip-flop with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The SN74LV175A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. 8.2 Functional Block Diagram Figure 8-1. Logic Diagram (Positive Logic) 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 8.3 Feature Description 8.3.1 Balanced CMOS 3-State Outputs This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the three states that these outputs can be in. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10-kΩ resistor can be used to meet these requirements. Unused 3-state CMOS outputs should be left disconnected. 8.3.2 Balanced CMOS Push-Pull Outputs This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected. 8.3.3 Latching Logic This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-flops, but include all logic circuits that act as volatile memory. When the device is powered on, the state of each latch is unknown. There is no default state for each latch at start-up. The output state of each latching logic circuit only remains stable as long as power is applied to the device within the supply voltage range specified in the Recommended Operating Conditions table. 8.4 Device Functional Modes Table 8-1. Function Table INPUTS OUTPUTS CLR CLK D QO Q L X X L H H ↑ H H L H ↑ L L H H L X Qo Q Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 11 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LV175A is a low-drive CMOS device that can be used for a multitude of bus interface type applications where the data needs to be retained or latched. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid VCC. This feature makes it Ideal for translating down to the VCC level. Figure 9-2 shows the reduction in ringing compared to higher drive parts such as the AC or LVC families of logic parts. 10 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for the best results. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in the Layout Example for SN74LV175A are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. 12 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A 13 SN74LV175A www.ti.com SCLS400H – APRIL 1998 – REVISED DECEMBER 2022 13 Trademarks All trademarks are the property of their respective owners. 14 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV175A PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV175AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples SN74LV175ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples SN74LV175ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples SN74LV175ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV175A Samples SN74LV175APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples SN74LV175APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples SN74LV175APWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV175A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of