SN74LV221AQPWRG4Q1

SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com DUAL MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN74LV221A-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications 2-V to 5.5-V VCC Operation Supports Mixed-Mode Voltage Operation on All Ports Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Transition Rates Overriding Clear Terminates Output Pulse Glitch-Free Power-Up Reset on Outputs Ioff Supports Partial-Power-Down Mode Operation PW PACKAGE (TOP VIEW) 1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A DESCRIPTION/ORDERING INFORMATION The SN74LV221A is a dual multivibrator designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input. This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext(positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the SN74LV221A-Q1 is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5. During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2008, Texas Instruments Incorporated SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com Table 1. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) TSSOP – PW ORDERABLE PART NUMBER Reel of 2000 SN74LV221AQPWRQ1 TOP-SIDE MARKING LV221AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DESCRIPTION/ORDERING INFORMATION (CONTINUED) Pin assignments are identical to those of the SN74AHC123A and SN74AHCT123A devices, so the SN74LV221A-Q1 can be substituted for those devices not using the retrigger feature. For additional application information on multivibrators, see the application report Designing With The SN74AHC123A and SN74AHCT123A, literature number SCLA014. FUNCTION TABLE (EACH MULTIVIBRATOR) INPUTS CLR (1) OUTPUTS A B Q Q FUNCTION L X X L H Reset H H X L H Inhibit H X L L H Inhibit H L ↑ Outputs enabled H ↓ H Outputs enabled ↑ (1) L H Outputs enabled This condition is true only if the output of the latch formed by the NAND gate has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high). LOGIC DIAGRAM (POSITIVE LOGIC) Rext/Cext A Cext B Q CLR 2 R Q Copyright © 2005–2008, Texas Instruments Incorporated SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com INPUT/OUTPUT TIMING DIAGRAM A B CLR Rext/Cext Q Q tw tw tw Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V –0.5 VCC + 0.5 V –0.5 7 (2) (3) UNIT VO Output voltage range in high or low state VO Output voltage range in power-off state (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA θJA Continuous current through VCC or GND ±50 mA Package thermal impedance (4) 108 °C/W ESD rating (5) Human-Body Model 2 (H2) Charged-Device Model 1 (C5) Machine Model Tstg (1) (2) (3) (4) (5) V Storage temperature range –65 kV 200 (M3) V 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. ESD protection level per AEC Q100 classification Copyright © 2005–2008, Texas Instruments Incorporated 3 SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com Recommended Operating Conditions (1) –40°C to 125°C VCC Supply voltage VCC = 2 V VIH High-level input voltage –40°C to 85°C MIN MAX 2 5.5 MIN MAX 2 5.5 1.5 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V UNIT V V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VIL Low-level input voltage VI Input voltage 0 5.5 0 5.5 VO Output voltage 0 VCC 0 VCC V –50 –50 μA VCC = 2.3 V to 2.7 V –2 –2 VCC = 3 V to 3.6 V –6 –6 –12 –12 VCC × 0.3 VCC = 4.5 V to 5.5 V VCC = 2 V IOH High-level output current VCC = 4.5 V to 5.5 V VCC = 2 V IOL Low-level output current Rext External timing resistance Cext External timing capacitance Δt/ΔVCC Power-up ramp rate TA Operating free-air temperature (1) 4 VCC × 0.3 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 6 6 VCC = 4.5 V to 5.5 V 12 5k 5k VCC ≥ 3 V 1k 1k No restriction No restriction 1 mA μA mA Ω pF 1 125 V 12 VCC = 2 V –40 V –40 ms/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright © 2005–2008, Texas Instruments Incorporated SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS IOH = –50 μA 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –6 mA IOH = –12 mA VOL VCC –40°C to 125°C MIN –40°C to 85°C TYP MAX MIN VCC – 0.1 VCC – 0.1 2 2 3V 2.48 2.48 4.5 V 3.8 TYP MAX V 3.8 IOL = 50 μA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 IOL = 12 mA 4.5 V II A, B, and CLR VI = 5.5 V or GND ICC Quiescent VI = VCC or GND, ICC Active state (per circuit) VI = VCC or GND, IO = 0 Rext/Cext = 0.5 VCC Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND UNIT 0.1 0.1 0.55 0.55 0 ±1 ±1 0 to 5.5 V ±1 ±1 5.5 V 20 20 3V 280 280 4.5 V 650 650 5.5 V 975 975 0 10 5 3.3 V 1.9 1.9 5V 1.9 1.9 V μA μA μA μA pF Timing Requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration MAX –40°C to 125°C MIN MAX –40°C to 85°C MIN CLR 5 7 5 A or B trigger 5 7 5 MAX UNIT ns Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN tw Pulse duration MAX –40°C to 125°C MIN MAX –40°C to 85°C MIN CLR 5 7 5 A or B trigger 5 7 5 Copyright © 2005–2008, Texas Instruments Incorporated MAX UNIT ns 5 SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE Q or Q CL = 50 pF MIN A or B tpd CLR CLR trigger CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ tw (1) Δtw (1) (2) Q or Q (2) –40°C to 125°C TA = 25°C –40°C to 85°C UNIT TYP MAX MIN MAX MIN MAX 11.8 24.1 1 30.5 1 27.5 10.6 19.3 1 25 1 22 12.3 25.9 1 32.5 1 29.5 186 240 340 ns 300 ns CL = 50 pF, Cext = 0.01 μF, Rext = 10 kΩ 90 100 110 85 115 90 110 μs CL = 50 pF, Cext = 0.1 pF, Rext = 10 kΩ 0.9 1 1.1 0.85 1.15 0.9 1.1 ms ±1 CL = 50 pF % tw = Pulse duration at Q and Q outputs Δtw = Output pulse-duration variation (Q and Q) between circuits in same package Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE Q or Q CL = 50 pF TA = 25°C MIN A or B tpd CLR CLR trigger CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ tw (1) Δtw (1) (2) Q or Q (2) TYP MAX –40°C to 125°C –40°C to 85°C MIN MAX MIN MAX UNIT 8.2 14 1 19 1 16 7.4 11.4 1 16 1 13 8.6 14.9 1 20 1 17 171 200 280 ns 240 ns CL = 50 pF, Cext = 0.01 μF, Rext = 10 kΩ 90 100 110 85 115 90 110 μs CL = 50 pF, Cext = 0.1 pF, Rext = 10 kΩ 0.9 1 1.1 0.85 1.15 0.9 1.1 ms ±1 CL = 50 pF % tw = Pulse duration at Q and Q outputs Δtw = Output pulse-duration variation (Q and Q) between circuits in same package Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 10 MHz VCC TYP 3.3 V 50 5V 51 UNIT pF Copyright © 2005–2008, Texas Instruments Incorporated SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION Test Point From Output Under Test tw VCC CL (see Note A) Inputs or Outputs 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION LOAD CIRCUIT VCC Input A (see Note B) 50% VCC 0V VCC Input B (see Note B) 50% VCC 50% VCC 0V 50% VCC tPLH 0V tPLH VOH In-Phase Output 50% VCC In-Phase Output VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS DELAY TIMES tPHL 50% VCC tPHL tPHL Out-of-Phase Output VCC Input CLR (see Note B) Out-of-Phase Output VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr + 3 ns, tf + 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Copyright © 2005–2008, Texas Instruments Incorporated 7 SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com APPLICATION INFORMATION Caution in Use To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible. Power-Down Considerations Large values of Cext can cause problems when powering down the SN74LV221A-Q1 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can discharge from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC × Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the SN74LV221A-Q1 can sustain damage. To avoid this possibility, use external clamping diodes. Output Pulse Duration The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing resistance (RT). The timing components are connected as shown in Figure 2. VCC RT CT To Rext/Cext Terminal To Cext Terminal Figure 2. Timing-Component Connections The pulse duration is given by: tw = K × RT × CT if CT is ≥ 1000 pF, K = 1.0 or if CT is < 1000 pF, K can be determined from Figure 7 where: tw = pulse duration in ns RT = external timing resistance in kΩ CT = external capacitancein pF K = multiplier factor (1) Equation 1 and Figure 3 or Figure 4 can be used to determine values for pulse duration, external resistance, and external capacitance. 8 Copyright © 2005–2008, Texas Instruments Incorporated SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com APPLICATION INFORMATION Operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 1.00E+07 VCC = 4.5 V TA = 25°C 1.00E+06 t w − Output Pulse Duration − ns t w − Output Pulse Duration − ns VCC = 3 V TA = 25°C RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.00E+04 RT = 10 kΩ 1.00E+03 1.00E+06 RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.00E+04 RT = 10 kΩ 1.00E+03 RT = 1 kΩ 1.00E+02 101 102 RT = 1 kΩ 103 104 1.00E+02 101 105 102 103 104 105 CT − External Timing Capacitance − pF CT − External Timing Capacitance − pF Figure 3. Figure 4. VARIATION IN OUTPUT PULSE DURATION vs TEMPERATURE 14% Variation in Output Pulse Duration 12% 10% tw = 866 ns at: VCC = 5 V RT = 10 kΩ CT = 50 pF TA = 25°C VCC = 2.5 V VCC = 3 V 8% VCC = 3.5 V VCC = 4 V 6% VCC = 5 V 4% VCC = 6 V VCC = 7 V 2% 0% −2% −4% −6% −60 −40 −20 0 20 40 60 80 100 120 140 160 180 Temperature − °C Figure 5. Copyright © 2005–2008, Texas Instruments Incorporated 9 SN74LV221A-Q1 SCLS692A – OCTOBER 2005 – REVISED APRIL 2008 www.ti.com EXTERNAL CAPACITANCE vs MULTIPLIER FACTOR OUTPUT PULSE DURATION CONSTANT vs SUPPLY VOLTAGE 1.15 0.001 RT = 10 kΩ TA = 25°C tw = K × CT × RT 1.10 C T − External Capacitor Value − µF Output Pulse Duration Constant − K 1.20 CT = 1000 pF 1.05 CT = 0.01 µF 1.00 CT = 0.1 µF 0.0001 0.95 0.00001 0.90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 For Capacitor Values of 0.001 µF or Greater, K = 1.0 (K is Independent of R) TA = 25°C VCC = 5 V 1.00 6 1.50 VCC − Supply Voltage − V 2.00 2.50 3.00 3.50 4.00 4.50 Multiplier Factor − K Figure 6. Figure 7. Relative Frequency of Occurrence DISTRIBUTION OF UNITS vs OUTPUT PULSE DURATION VCC = 5 V TA = 25°C CT = 50 pF RT = 10 kΩ Mean = 856 ns Median = 856 ns Std. Dev. = 3.5 ns −3 Std. Dev. 99% of Data Units +3 Std. Dev. Median tw − Output Pulse Duration Figure 8. 10 Copyright © 2005–2008, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV221AQPWRG4Q1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV221AQ SN74LV221AQPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV221AQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of