SN74LV244APW

SN74LV244A SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 SN74LV244A Octal Buffers and Drivers With 3-State Outputs 1 Features 3 Description • • • The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V VCC operation. • • • • VCC operation of 2 V to 5.5 V Maximum tpd of 6.5 ns at 5 V Typical VOLP (output ground bounce) 2.3 V at VCC = 3.3 V, TA = 25°C Support mixed-mode voltage operation on all ports Ioff supports partial-power-down mode operation Latch-up performance exceeds 250-mA per JESD 17 The SN74LV244A devices are designed specifically to improve both performance and density of the 3state memory address drivers, clock drivers, and busoriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. Package Information(1) PART NUMBER 2 Applications • • • • Servers and network switches LED displays Telecom infrastructure Motor-drive control boards SN74LV244A (1) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 PACKAGE BODY SIZE (NOM) DGV (TVSOP, 20) 5.00 mm × 4.40 mm DW (SOIC, 20) 12.80 mm × 7.50 mm NS (SO, 20) 12.60 mm × 5.30 mm PW (TSSOP, 20) 6.50 mm × 4.40 mm RGY (VQFN, 20) 4.50 mm × 3.50 mm RKS (VQFN, 20) 4.50 mm × 2.50 mm For all available packages, see the orderable addendum at the end of the data sheet. 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 Logic Diagram (Positive Logic) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................6 6.6 Noise Characteristics.................................................. 6 6.7 Operating Characteristics........................................... 6 6.8 Switching Characteristics: VCC = 2.5 V ± 0.2 V...........7 6.9 Switching Characteristics: VCC = 3.3 V ± 0.3 V...........7 6.10 Switching Characteristics: VCC = 5 V ± 0.5 V............7 6.11 Typical Characteristics.............................................. 8 7 Parameter Measurement Information............................ 9 8 Detailed Description......................................................10 8.1 Overview................................................................... 10 8.2 Functional Block Diagram......................................... 10 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................12 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Application.................................................... 13 10 Power Supply Recommendations..............................16 11 Layout........................................................................... 16 11.1 Layout Guidelines................................................... 16 11.2 Layout Example...................................................... 16 12 Device and Documentation Support..........................17 12.1 Documentation Support.......................................... 17 12.2 Receiving Notification of Documentation Updates..17 12.3 Support Resources................................................. 17 12.4 Trademarks............................................................. 17 12.5 Electrostatic Discharge Caution..............................17 12.6 Glossary..................................................................17 13 Mechanical, Packaging, and Orderable Information.................................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (September 2015) to Revision O (December 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added the RKS package to the data sheet.........................................................................................................1 • Updated the Typical Characteristics section.......................................................................................................8 • Added the Balanced CMOS 3-State Outputs, Standard CMOS Inputs, Partial Power Down (Ioff), and Clamp Diode Structure sections...................................................................................................................................10 • Removed the Design Requirements section.................................................................................................... 13 • Added the Power Considerations, Input Considerations, and Output Considerations sections....................... 13 • Updated the Detailed Design Procedure section..............................................................................................15 • Updated the Power Supply Recommendations section....................................................................................16 • Updated the Layout Guidelines and Layout Example section.......................................................................... 16 Changes from Revision M (June 2013) to Revision N (September 2015) Page • Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Detailed Description section, Applications and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............................................................................................................................................. 1 • Deleted SN54LV244A part number from the data sheet.................................................................................... 1 • Removed the TA = –40°C to 85°C test conditions with the same values as the TA = –40°C to 125°C Recommended test conditions in the Electrical Characteristics and Switching Characteristics tables ............. 6 • Removed the word 'Recommended' in the TA = –40°C to 125°C Recommended test conditions in the Electrical Characteristics and Switching Characteristics tables .........................................................................6 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 5 Pin Configuration and Functions Figure 5-1. DB, DGV, DW, NS, PW Package, 20-Pin SSOP, TVSOP, SOIC, SO, TSSOP (Top View) Figure 5-2. RGY and RKS Package, 20-Pin VQFN With Exposed Thermal Pad (Top View) Table 5-1. Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION 1A1 2 I Input 1A2 4 I Input 1A3 6 I Input 1A4 8 I Input 1 OE 1 I Output enable 1Y1 18 O Output 1Y2 16 O Output 1Y3 14 O Output 1Y4 12 O Output 2A1 11 I Input 2A2 13 I Input 2A3 15 I Input 2A4 17 I Input 2 OE 19 I Output enable 2Y1 9 O Output 2Y2 7 O Output 2Y3 5 O Output 2Y4 3 O Output GND 10 — Ground VCC 20 — Power pin — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply. Thermal (1) (2) pad(2) Signal Types: I = Input, O = Output, I/O = Input or Output RKS package only Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 3 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC MIN MAX Supply voltage –0.5 7 V voltage(2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 VI Input VO Voltage range applied to any output in the high-impedance or power-off state(2) voltage(2) (3) UNIT VO Output IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±35 mA Continuous current through VCC or GND V ±70 mA Tj Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5-V maximum. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage VCC = 2 V VIH High-level input voltage MIN MAX 2 5.5 Low-level input voltage VI Input voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 Output voltage VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 High-level output current 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 2.3 V to 2.7 V –2 VCC = 3 V to 3.6 V –8 Δt/Δv Input transition rise or fall rate (1) µA mA 50 VCC = 2.3 V to 2.7 V 2 VCC = 3 V to 3.6 V 8 VCC = 4.5 V to 5.5 V 16 VCC = 2.3 V to 2.7 V 200 VCC = 3 V to 3.6 V 100 VCC = 4.5 V to 5.5 V TA V –16 VCC = 2 V Low-level output current V –50 VCC = 4.5 V to 5.5 V IOL V VCC × 0.3 0 VCC = 2 V IOH V 0.5 VCC = 4.5 V to 5.5 V VO V 1.5 VCC = 2 V VIL UNIT µA mA ns/V 20 Operating free-air temperature –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 6.4 Thermal Information SN74LV244A THERMAL METRIC(1) DB (SSOP) DGV (TVSOP) DW (SOIC) NS (SO) PW (TSSOP) RGY (VQFN) RKS (VQFN) UNIT 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS RθJA Junction-to-ambient thermal resistance 94.7 115.9 79.4 76.9 102.6 34.9 75.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.7 31.1 43.8 43.4 36.7 43.1 79.4 °C/W RθJB Junction-to-board thermal resistance 49.9 57.4 47.2 44.5 53.6 12.7 47.8 °C/W ψJT Junction-to-top characterization parameter 18.7 1.0 18.8 17.0 2.4 0.9 14.6 °C/W ψJB Junction-to-board characterization parameter 49.5 56.7 46.7 44.1 53.1 12.8 47.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a 7.8 31.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 5 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS High level output voltage VOL Low level output voltage VCC MIN TYP MAX UNIT IOH = –50 µA 2 V to 5.5 V VCC – 0.1 IOH = –2 mA 2.3 V 2 IOH = –8 mA 3V 2.48 IOH = 16 mA 4.5 V 3.8 IOL = 50 µA 2 V to 5.5 V IOL = 2 mA 2.3 V 0.4 IOL = 8 mA 3V 0.44 IOL = 16 mA 4.5 V 0.55 ±1 µA V 0.1 V II Input leakage current VI = 5.5 V or GND 0 to 5.5 V IOZ Off-State (High-Impedance State) Output Current (of a 3-State Output) VO = VCC or GND 5.5 V ±5 µA ICC Supply current VI = VCC or GND, IO = 0 5.5 V 20 µA Ioff Input/Output Power-Off Leakage Current VI or VO = 0 to 5.5 V 5 µA Ci Input capacitance VI = VCC or GND 0 3.3 V 2.3 pF 6.6 Noise Characteristics VCC = 3.3 V, CL = 50 pF, TA = 25°C(1) MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic 0.55 V VOL(V) Quiet output, minimum dynamic –0.5 V VOH(V) Quiet output, minimum dynamic 2.9 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 2.31 V 0.99 V Characteristics are for surface-mount packages only. 6.7 Operating Characteristics TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS CL = 50 pF f = 10 MHz Submit Document Feedback VCC TYP UNIT 3.3 V 14 5V 16 pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.8 Switching Characteristics: VCC = 2.5 V ± 0.2 V over operating free-air temperature range (unless otherwise noted), (see Figure 7-1) PARAMETE R FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tsk(o) LOAD CAP 25°C MIN –40°C to 125°C TYP MAX MIN CL = 15 pF 7.5 12.5 1 15 CL = 50 pF 9.5 15.3 1 18 CL = 15 pF 8.9 14.6 1 17 CL = 50 pF 10.8 17.8 1 21 CL = 15 pF 9.1 14.1 1 16 CL = 50 pF 13.4 19.2 1 21 CL = 50 pF TYP 2 MAX 2 UNIT ns ns ns ns 6.9 Switching Characteristics: VCC = 3.3 V ± 0.3 V over operating free-air temperature range (unless otherwise noted), (see Figure 7-1) PARAMETE R FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tsk(o) LOAD CAP 25°C MIN –40°C to 125°C TYP MAX MIN CL = 15 pF 5.4 8.4 1 10 CL = 50 pF 6.8 11.9 1 13.5 CL = 15 pF 6.3 10.6 1 12.5 CL = 50 pF 7.8 14.1 1 16 CL = 15 pF 7.6 11.7 1 13 CL = 50 pF 11 16 1 18 CL = 50 pF TYP 1.5 MAX 1.5 UNIT ns ns ns ns 6.10 Switching Characteristics: VCC = 5 V ± 0.5 V over operating free-air temperature range (unless otherwise noted), (see Figure 7-1) PARAMETE R FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tsk(o) LOAD CAP 25°C MIN –40°C to 125°C TYP MAX MIN CL = 15 pF 3.9 5.5 1 6.5 CL = 50 pF 4.9 7.5 1 8.5 CL = 15 pF 4.5 7.3 1 8.5 CL = 50 pF 5.6 9.3 1 10.5 CL = 15 pF 6.5 12.2 1 13.5 CL = 50 pF 8.8 14.2 1 15.5 CL = 50 pF 1 TYP MAX 1 UNIT ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 7 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 6.11 Typical Characteristics 0.16 0.3 0.14 0.25 0.12 0.2 VOL (V) VOL (V) 0.1 0.08 0.06 0.15 0.1 0.04 0.02 0.05 VCC = 2.3 V VCC = 3 V 0 0 2 4 IOL (mA) 6 0 8 Figure 6-1. Output Voltage in LOW state, 2.3- and 3-V Supply 2.9 2.8 VOH (V) VOH (V) 2.7 2.6 2.5 2.4 2.3 2.2 VCC = 2.3 V VCC = 3 V 2 -8 -6 -4 IOH (mA) -2 0 Figure 6-3. Output Voltage in HIGH state, 2.3- and 3-V Supply 6 8 IOL (mA) 10 12 14 16 5.5 5.4 5.3 5.2 5.1 5 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4 -16 VCC = 4.5 V VCC = 5.5 V -14 -12 -10 -8 IOH (mA) -6 -4 -2 0 0.6 VCC = 2.5 V 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 VCC = 3.3 V VCC = 5 V 0.54 ICC - Supply Current (mA) ICC - Supply Current (mA) 4 Figure 6-4. Output Voltage in HIGH state, 4.5- and 5.5-V Supply 0.1 0.09 0.48 0.42 0.36 0.3 0.24 0.18 0.12 0.06 0 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VI - Input Voltage (V) 2 2.25 2.5 Figure 6-5. Supply Current across Input Voltage, 2.5-V Supply 8 2 Figure 6-2. Output Voltage in LOW state, 4.5- and 5.5-V Supply 3 2.1 VCC = 4.5 V VCC = 5.5 V 0 0 0.5 1 1.5 2 2.5 3 3.5 VI - Input Voltage (V) 4 4.5 5 5.5 Figure 6-6. Supply Current across Input Voltage, 3.3- and 5-V Supply Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 7 Parameter Measurement Information A. B. C. D. E. F. G. H. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. The outputs are measured one at a time, with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPHL and tPLH are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 7-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 9 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 8 Detailed Description 8.1 Overview The SN74LV244 devices are octal buffers grouped in fours, with each group having its own enable pin. The LV family supports high current drive of about 16 mA, thus making it suitable for driving digital signals over longer board lengths. This device is generally used to buffer or incorporate delays between the signals between two microcontroller or peripheral devices. 8.2 Functional Block Diagram 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 8.3 Feature Description 8.3.1 Balanced CMOS 3-State Outputs This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the three states that these outputs can be in. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10-kΩ resistor can be used to meet these requirements. Unused 3-state CMOS outputs should be left disconnected. 8.3.2 Standard CMOS Inputs This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in Implications of Slow or Floating CMOS Inputs. Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A www.ti.com SN74LV244A SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a 10-kΩ resistor, however, is recommended and will typically meet all requirements. 8.3.3 Partial Power Down (Ioff) This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage current at each output is defined by the Ioff specification in the Electrical Characteristics table. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 11 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 8.3.4 Clamp Diode Structure Figure 8-1 shows the inputs and outputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed. Device VCC Logic Input Output -IIK -IOK GND Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output 8.4 Device Functional Modes The SN74LV244A devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Table 8-1. Function Table INPUTS(1) (1) (2) 12 OUTPUTS(2) OE A Y L L L L H H H X Z H = High Voltage Level, L = Low Voltage Level, X = Do Not Care H = Driving High, L = Driving Low, Z = High Impedance State Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SN74LV244A device can be used as an 8-channel buffer to drive signals from one controller to another device. Buffers are typically used for signals running on long traces on printed circuit boards or going through connectors linking two printed circuit boards together. Buffers are also used to create delay between the lines to match the edges of two clock or data signals. The high-current capability of the SN74LV244A device also allows a controller to drive LEDs up to 16 mA. 9.2 Typical Application Figure 9-1. Typical Application Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 13 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 9.2.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74LV244A plus the maximum static supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74LV244A plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN74LV244A can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50 pF. The SN74LV244A can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. 9.2.2 Input Considerations Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74LV244A (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor value is often used due to these factors. The SN74LV244A has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. Refer to the Feature Description section for additional information regarding the inputs for this device. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 9.2.3 Output Considerations The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. 9.2.4 Detailed Design Procedure 1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74LV244A to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. 9.2.5 Application Curve Figure 9-2. SN74LV244A Transient response Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 15 SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for best results. 11 Layout 11.1 Layout Guidelines When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 11.2 Layout Example VCC Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation 1OE 1 VCC GND 0.1
F Bypass capacitor placed close to the device 1A1 2 20 19 2Y4 3 18 1Y1 Unused input tied to GND 1A2 4 17 2A4 2Y3 5 16 1Y2 Unused output 1A3 6 15 2A3 1Y3 Avoid 90° corners for signal lines GND 2OE left floating 2Y2 7 14 1A4 8 13 2A2 2Y1 9 10 12 11 1Y4 GND 2A1 Figure 11-1. Layout Example for the SN74LV244A in the RKS Package 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A SN74LV244A www.ti.com SCLS383O – SEPTEMBER 1997 – REVISED DECEMBER 2022 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • • • Texas Instruments, CMOS Power Consumption and Cpd Calculation Texas Instruments, Implications of Slow or Floating CMOS Inputs application notes Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN74LV244A 17 PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LV244ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADBRE4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ADWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV244A Samples SN74LV244APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWRG3 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV244A Samples SN74LV244ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LV244A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2022 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of