SN74LV244ATDBR

SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 18 3 4 5 17 6 7 15 8 9 13 12 10 11 16 14 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 VCC RGY PACKAGE (TOP VIEW) DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 1 20 19 2OE 18 1Y1 17 2A4 2 3 4 6 16 1Y2 15 2A3 7 8 14 1Y3 13 2A2 9 12 1Y4 5 10 11 2A1 • • 1OE • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd = 5.4 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports GND • • • • DESCRIPTION/ORDERING INFORMATION This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. ORDERING INFORMATION PACKAGE (1) TA QFN – RGY Tube of 25 SN74LV244ATDW Reel of 2000 SN74LV244ATDWR SOP – NS Reel of 2000 SN74LV244ATNSR 74LV244AT SSOP – DB Reel of 2000 SN74LV244ATDBR LV244AT Tube of 70 SN74LV244ATPW Reel of 2000 SN74LV244ATPWR Reel of 250 SN74LV244ATPWT Reel of 2000 SN74LV244ATDGVR TSSOP – PW TVSOP – DGV (1) TOP-SIDE MARKING SN74LV244ATRGYR SOIC – DW –40°C to 85°C ORDERABLE PART NUMBER Reel of 1000 VV244 LV244AT LV244AT LV244AT Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (EACH 4-BIT BUFFER/DRIVER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range applied in the high or low state (2) (3) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA Continuous current through VCC or GND DB θJA Package thermal impedance package (4) 70 DGV package (4) 92 DW package (4) 58 NS package (4) 60 PW package (4) 83 RGY package (5) Tstg (1) (2) (3) (4) (5) Storage temperature range V °C/W 37 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7 The package thermal impedance is calculated in accordance with JESD 51-5. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V VI Input voltage MIN MAX 4.5 5.5 2 UNIT V V 0.8 V 0 5.5 V High or low state 0 VCC 3-state 0 5.5 VO Output voltage IOH High-level output current VCC = 4.5 V to 5.5 V –16 IOL Low-level output current VCC = 4.5 V to 5.5 V 16 mA ∆t/∆v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 ns/V TA Operating free-air temperature 85 °C (1) –40 V mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TA = –40°C to 85°C TA = 25°C VCC MIN TYP 4.5 IOH = –50 µA 4.5 V 4.4 IOH = –16 mA 4.5 V 3.8 IOL = 50 µA 4.5 V IOL = 16 mA 4.5 V MAX MIN UNIT MAX 4.4 V 3.8 0 0.1 0.1 0.55 0.55 V II VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 2 20 µA One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 mA 0 0.5 5 µA ∆ICC (1) TEST CONDITIONS (1) Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND 4.5 pF This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A or B B or A CL = 15 pF OE A or B CL = 15 pF OE A or B CL = 15 pF A or B B or A CL = 50 pF OE A or B CL = 50 pF OE A or B CL = 50 pF tsk(o) TA = 25°C MIN MIN MAX TYP MAX 2.6 5/4 7.4 1 8.5 2.4 5.4 7.4 1 8.5 2.2 7.7 10.4 1 12 2.7 7.7 10.4 1 12 2.2 3.9 7.7 1 8 2.5 3.9 7.7 1 8 4 5.9 8.9 1 9.5 4.7 5.9 8.9 1 9.5 3.9 8.2 11.4 1 13 4.9 8.2 11.4 1 13 3.3 8.8 11.4 1 13 3.2 8.8 11.4 1 13 CL = 50 pF 1 1 UNIT ns ns ns ns ns ns ns Noise Characteristics (1) VCC = 5 V, CL = 50 pF PARAMETER TA = 25°C MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.8 1 V VOL(V) Quiet output, minimum dynamic VOL –0.8 –1 V VOH(V) Quiet output, minimum dynamic VOH 4 VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 4 Characteristics are for surface-mount packages only. V 2 V 0.8 V SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled CL = 50 pF, f = 10 MHz TYP 8 UNIT pF 5 SN74LV244AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES572C – JUNE 2004 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LV244ATDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV244AT SN74LV244ATNSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 74LV244AT SN74LV244ATPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV244AT SN74LV244ATPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV244AT SN74LV244ATRGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VV244 SN74LV244ATRGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 VV244 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LV244ATDWR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DW 20 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 13.3 2.7 12.0 24.0 Q1 SN74LV244ATNSR SO NS 20 2000 330.0 24.4 9.0 13.0 2.4 12.0 24.0 Q1 SN74LV244ATPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244ATRGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV244ATDWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LV244ATNSR SO NS 20 2000 367.0 367.0 45.0 SN74LV244ATPWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LV244ATRGYR VQFN RGY 20 3000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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