SN74LV367A
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
SN74LV367A Hex Buffers and Line Drivers With 3-State Outputs
1 Applications
3 Description
•
•
•
The ’LV367A devices are hex buffers and line drivers
designed for 2 V to 5.5 V VCC operation.
Output expansion
LED matrix control
7-segment display control
Package Information(1)
2 Features
•
•
•
•
•
•
PART NUMBER
Operation of 2 V to 5.5 VCC
Maximum tpd of 7 ns at 5 V
Typical VOLP (output ground bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250 mA per JESD
17
SN74LV367A
(1)
PACKAGE
BODY SIZE (NOM)
D (SOIC, 16)
9 mm × 3.90 mm
DB (SSOP, 16)
6.50 mm × 5.30 mm
DGV (TVSOP ,16)
3.60 mm × 4.40 mm
NS (SOP, 16)
10.20 mm x 5.30 mm
PW (TSSOP, 16)
5.00 mm x 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
Table of Contents
1 Applications..................................................................... 1
2 Features............................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........7
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........7
6.8 Switching Characteristics, VCC = 5 V ± 0.5 V..............7
6.9 Noise Characteristics.................................................. 7
6.10 Operating Characteristics......................................... 8
6.11 Typical Characteristics.............................................. 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................12
9 Application and Implementation.................................. 13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.4 Trademarks............................................................. 15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 1998) to Revision H (December 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
5 Pin Configurations and Functions
Figure 5-1. D, DGV, NS, or PW Package (Top View)
Table 5-1. Pin Functions
PIN
NO.
NAME
1
1 OE
2
3
4
5
6
7
TYPE
DESCRIPTION
I
Output Enable 1
1A1
I
1A1 Input
1Y1
O
1Y1 Output
1A2
I
1A2 Input
1Y2
O
1Y2 Output
1A3
I
1A3 Input
1Y3
O
1Y3 Output
8
GND
—
Ground Pin
9
1Y4
O
1Y4 Output
10
1A4
I
1A4 Input
11
2Y1
O
2Y1 Output
12
2A1
I
2A1 Input
13
2Y2
O
2Y2 Output
14
2A2
I
2A2 Input
15
2 OE
I
Output Enable 2
16
VCC
—
Power Pin
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
3
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
range(2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Voltage range applied to any output in the
high-impedance or power-off state(2)
VO
Output voltage range applied in the high or low state(2) (3)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
±2000
Machine Model (MM), per JEDEC specification
±200
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002
(1)
(2)
4
UNIT
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VO
Output voltage
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
–50
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–8
VCC = 4.5 V to 5.5 V
Low-level output current
Δt/Δv
Input transition rise or fall rate
50
VCC = 2.3 V to 2.7 V
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
V
V
µA
mA
–16
VCC = 2 V
IOL
V
VCC × 0.3
0
VCC = 2 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
µA
mA
ns/V
20
Operating free-air temperature
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74LV367A
THERMAL
RθJA
(1)
METRIC(1)
Junction-to-ambient thermal
resistance
D
DB
DGV
NS
PW
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
73
82
120
64
108
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
5
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
2 V to 5.5 V
IOH = –2 mA
2.3 V
IOH = –8 mA
3V
2.48
4.5
3.8
TYP
MAX
UNIT
VCC – 0.1
2
V
IOL = 50 µA
2 V to 5.5 V
IOL = 2 mA
2.3 V
0.4
IOL = 8 mA
3V
0.44
4.5 V
0.55
IOL = 16 mA
6
SN74LV367A
MIN
IOH = –50 µA
IOH = –16 mA
VOL
VCC
0.1
V
II
VI= 5.5 V or GND
0 to 5.5 V
±1
µA
IOZ
VO = VCC or GND
5.5 V
±5
µA
ICC
VI = VCC or GND, IO = 0
20
µA
Ioff
VO= or VO = 0 to 5.5 V
5
µA
Ci
VI = VCC or GND
3.3 V
3
pF
CO
VI = VCC or GND
3.3 V
5.2
pF
5.5 V
0
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
6.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
tpd
A
ten
tdis
PARAMETER
LOAD
CAPACITANCE
TA = 25°C
MIN
SN74LV367A
TYP
MAX
MIN
MAX
6.4
12.7
1
16
6.9
14.9
1
20
Y
6.4
14.9
1
20
Y
8.6
17.5
1
21
OE
Y
9.4
19.7
1
25
OE
Y
10.1
19.7
1
25
CL = 15 pF
CL = 50 pF
tsk(o)
2
UNIT
ns
ns
2
6.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
tpd
A
ten
OE
tdis
OE
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN74LV367A
TYP
MAX
MIN
MAX
4.7
8.3
1
10
5.1
10.5
1
12.5
4.9
10.5
1
12.5
Y
6.2
11.8
1
13.5
Y
6.8
14
1
16
7.3
13.6
1
15.5
CL = 15 pF
CL = 50 pF
tsk(o)
1.5
UNIT
ns
ns
1.5
6.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted)
LOAD
CAPACITANCE
TA = 25°C
SN74LV367A
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
2.6
tpd
A
Y
4.5
7.9
1
9
ten
OE
Y
4.9
9.2
1
10.5
tdis
OE
Y
4.5
9.2
0
10.5
PARAMETER
MIN
CL = 15 pF
CL = 50 pF
tsk(o)
TYP
MAX
MIN
3.6
5.9
1
7
3.8
7.2
1
8.5
0
8.5
7.2
MAX
1
UNIT
ns
ns
1
6.9 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
PARAMETER
MIN
0.3
0.8
UNIT
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
V
2.31
V
0.99
V
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
7
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
14.9
5V
17.4
UNIT
pF
6.11 Typical Characteristics
13
CL=50pF
12
tPD (ns)
11
10
9
8
7
6
2.5
3
3.5
4
VCC (V)
4.5
5
C001
Figure 6-1. TPD vs VCC
8
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
7 Parameter Measurement Information
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
tPHL
50% VCC
tPHL
50% VCC
VOL
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
A.
B.
C.
D.
E.
F.
G.
H.
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
50% VCC
tPLZ
tPZL
VOH
In-Phase
Output
Out-of-Phase
Output
0V
VCC
Output
Control
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
The outputs are measured one at a time, with one input transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
tPHL and tPLH are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
9
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
8 Detailed Description
8.1 Overview
The ’LV367A devices are hex buffers and line drivers designed for 2 V to 5.5 V VCC operation. These devices
are designed specifically to improve both the performance and density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE
and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When
OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
Figure 8-1. Logic Diagram (Positive Logic)
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10-kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.4 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.5 Clamp Diode Structure
Figure 8-2 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
11
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Buffer/ Driver)
INPUTS
12
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV595A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs are 5-V tolerant allowing for down translation to VCC.
9.2 Typical Application
Figure 9-1. Expanding IOs to Drive LEDs
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
13
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because
the undefined voltages at the outside connections result in undefined operational states. All unused inputs of
digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage
specifications, to prevent them from floating. The logic level that must be applied to any particular unused input
depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more
sense for the logic function or is more convenient.
11.2 Layout Example
Figure 11-1. Layout Example for the SN74LV367A
14
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
SN74LV367A
www.ti.com
SCLS398H – APRIL 1998 – REVISED DECEMBER 2022
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV367A
15
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV367AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
SN74LV367ADE4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
SN74LV367ADGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
SN74LV367ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
SN74LV367ANSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV367A
Samples
SN74LV367APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
SN74LV367APWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV367A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
