SN74LV373ATRGYRG4

SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) xxxxxxx OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 RGY PACKAGE (TOP VIEW) VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q VCC DB, DW, NS, OR PW PACKAGE (TOP VIEW) 1 20 3 4 19 8Q 18 8D 17 7D 5 6 16 7Q 15 6Q 7 8 14 6D 13 5D 9 12 5Q 2 10 11 LE • • OE • Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Typical tpd of 5.1 ns at 5 V Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 5 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports GND • • • • DESCRIPTION/ORDERING INFORMATION The SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. ORDERING INFORMATION PACKAGE (1) TA QFN – RGY Tube of 25 SN74LV373ATDW Reel of 2500 SN74LV373ATDWR SOP – NS Reel of 2000 SN74LV373ATNSR 74LV373AT SSOP – DB Reel of 2000 SN74LV373ATDBR LV373AT Tube of 70 SN74LV373ATPW Reel of 2000 SN74LV373ATPWR Reel of 250 SN74LV373ATPWT TSSOP – PW (1) TOP-SIDE MARKING SN74LV373ATRGYR SOIC – DW –40°C to 125°C ORDERABLE PART NUMBER Reel of 1000 VV373 LV373AT LV373AT Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (EACH LATCH) INPUTS OE LE D OUTPUT Q H l H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) OE LE 1 11 C1 1D 3 1D To Seven Other Channels 2 2 1Q SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±50 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA Continuous current through VCC or GND package (4) 70 DW package (4) 58 NS package (4) 60 PW package (4) 83 DB θJA Package thermal impedance RGY package (5) Tstg (1) (2) (3) (4) (5) Storage temperature range V °C/W 37 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V VI Input voltage MIN MAX 4.5 5.5 2 UNIT V V 0.8 V V 0 5.5 High or low state 0 VCC 3-state 0 5.5 VO Output voltage IOH High-level output current VCC = 4.5 V to 5.5 V –16 IOL Low-level output current VCC = 4.5 V to 5.5 V 16 mA ∆t/∆v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 ns/V TA Operating free-air temperature 125 °C (1) –40 V mA All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II TA = 25°C VCC MIN TYP 4.5 IOH = –50 µA 4.5 V 4.4 IOH = –16 mA 4.5 V 3.8 IOL = 100 µA 4.5 V IOL = 16 mA 4.5 V VI = 5.5 or GND IOZ VO = VCC or GND ICC VI = VCC or GND, ∆ICC (1) (1) TEST CONDITIONS IO = 0 One input at 3.4 V, Other inputs at VCC or GND Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND Co VO = VCC or GND TA = –40°C to 85°C TA = –40°C to 125°C MIN MAX MIN MAX MAX 0 4.4 4.4 3.8 3.8 UNIT V 0.1 0.1 0.1 0.55 0.55 0.55 V 0 to 5.5 V ±0.1 ±1 ±1 µA 5.5 V ±0.25 ±2.5 ±2.5 µA 5.5 V 2 20 20 µA 5.5 V 40 50 50 µA 0 0.5 5 5 µA 10 10 10 pF 4 7.5 pF This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = –40°C to 85°C TA = 25°C MIN MAX MIN TA = –40°C to 125°C MAX UNIT MIN MAX tw Pulse duration, LE high 6.5 8.5 8.5 ns tsu Setup time, data before LE↓ High or low 1.5 1.5 1.5 ns th Hold time, data after LE↓ High or low 3.5 3.5 3.5 ns Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd TO (OUTPUT) D Q LOAD CAPACITANCE TA = –40°C to 85°C TA = 25°C MIN TYP MAX MIN MAX TA = –40°C to 125°C MIN MAX 2.9 5.1 8.5 1 9.5 1 10 3.5 7.7 12.3 1 13.5 1 14 3.5 6.3 10.9 1 12.5 1 13 LE Q ten OE Q tdis OE Q 1.7 3.3 7.2 1 8.5 1 9 D Q 4.4 5.9 9.5 1 10.5 1 11 4.8 8.5 13.3 1 14.5 1 15 5 7.1 11.9 1 13.5 1 14 3 8.8 11.2 1 12 1 12.5 tpd LE Q ten OE Q tdis OE Q tsk(o) 4 FROM (INPUT) CL = 15 pF CL = 50 pF 1 1 UNIT ns ns SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 Noise Characteristics (1) VCC = 5 V, CL = 50 pF, TA = 25°C TYP MAX VOL(P) Quiet output, maximum dynamic VOL PARAMETER 0.8 1 V VOL(V) Quiet output, minimum dynamic VOL –0.6 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D)I High-level dymanic input voltage VIL(D) Low-level dynamic input voltage (1) MIN 2.9 UNIT V 2.31 V 0.99 V Characteristics are for surface-mount packages only. Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance Outputs enabled TEST CONDITIONS CL = 50 pF, f = 10 MHz TYP UNIT 15.5 pF 5 SN74LV373AT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES630B – JULY 2005 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LV373ATDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV373AT SN74LV373ATNSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 74LV373AT SN74LV373ATPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LV373AT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of