SN74LV374A
SCLS408K – APRIL 1998 – REVISED DECEMBER 2022
SN74LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
1 Features
3 Description
•
•
•
The SN74LV374A devices are octal edge-triggered Dtype flip-flops designed for 2 V to 5.5 V VCC operation.
•
•
•
•
VCC operation of 2 V to 5.5 V
Maximum tpd of 9.5 ns at 5 V
Typical VOLP (Output Ground Bounce) 2.3 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-up Performance Exceeds 250 mA Per JESD
17
Package Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LV374ADB
SSOP (20)
7.20 mm × 5.30 mm
SN74LV374ADW
SOIC (20)
12.80 mm × 7.50 mm
SN74LV374ANS
SO (20)
12.60 mm × 5.30 mm
SN74LV374APW
TSSOP (20)
6.50 mm × 4.40 mm
2 Applications
•
•
•
•
•
Programmable Logic Controller (PLC)
DCS and PAC: Analog Input Module
Trains, Trams, and Subway Carriages
AC Inverter Drives
Printers
Pin numbers shown are for the DB, DW, NS, PW, and RGY
packages.
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74LV374A
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SCLS408K – APRIL 1998 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
5 Pin Configuration and Functions...................................2
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V...........6
6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V...........7
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V..............7
6.9 Timing Requirements.................................................. 7
6.10 Noise Characteristics................................................ 8
6.11 Operating Characteristics, TA = 25°C........................8
6.12 Typical Characteristics.............................................. 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
9 Power Supply Recommendations................................13
10 Layout...........................................................................14
10.1 Layout Guidelines................................................... 14
10.2 Layout Example...................................................... 14
11 Device and Documentation Support..........................15
11.1 Documentation Support.......................................... 15
11.2 Related Links.......................................................... 15
11.3 Receiving Notification of Documentation Updates.. 15
11.4 Community Resources............................................15
11.5 Trademarks............................................................. 15
4
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2015) to Revision K (December 2022)
Page
• Updated the format for tables, figures, and cross-references throughout the document....................................1
Changes from Revision I (March 2015) to Revision J (October 2016)
Page
• Added Junction temperature, TJ ........................................................................................................................ 4
• Deleted "VCC × 0.3" from MIN and added "VCC × 0.3" to MAX for SN54LV374A and SN74LV374A..................5
• Changed "SN54LV384A" to "SN54LV374A" in Electrical Characteristics table.................................................. 6
• Added Related Links section, Receiving Notification of Documentation Updates section, and Community
Resources section............................................................................................................................................ 15
Changes from Revision H (April 2005) to Revision I (March 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
5 Pin Configuration and Functions
Figure 5-1. DB, DW, NS, or PW Package 20-PIN SSOP, SOIC, SO, or TSSOP Top View
2
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Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
OE
1
I
Enable pin
1Q
2
O
Output 1
1D
3
I
Input 1
2D
4
I
Input 2
2Q
5
O
Output 2
3Q
6
O
Output 3
3D
7
I
Input 3
4D
8
I
Input 4
4Q
9
O
Output 4
GND
10
–
Ground pin
CLK
11
I
Clock pin
5Q
12
O
Output 5
5D
13
I
Input 5
6D
14
I
Input 6
6Q
15
O
Output 6
7Q
16
O
Output 7
7D
17
I
Input 7
8D
18
I
Input 8
8Q
19
O
Output 8
VCC
20
–
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage
−0.5
7
V
voltage(2)
−0.5
7
V
−0.5
7
V
−0.5
VCC + 0.5
VI
Input
VO
Voltage applied to any output in the high-impedance or power-off state (2)
voltage(2) (3)
UNIT
VO
Output
IIK
Input clamp current, (VI < 0)
–20
mA
V
IOK
Output clamp current, (VO < 0)
–50
mA
IO
Continuous output current, (VO = 0 to VCC)
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
Machine Model (A115-A)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74LV374A
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VI
Input voltage
VO
Output voltage
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
−50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
–8
50
VCC = 2.3 V to 2.7 V
μA
mA
μA
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
(1)
V
–16
VCC = 2 V
Low-level output current
V
–2
VCC = 4.5 V to 5.5 V
IOL
V
VCC × 0.3
0
VCC = 2 V
IOH
V
VCC × 0.77
VCC = 2 V
Low-level input voltage
V
1.5
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
VIL
UNIT
mA
ns/V
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LV374A
THERMAL
RθJA
METRIC(1)
DW (SOIC)
NS (SO)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
94.5
79.2
76.7
102.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
56.4
43.7
43.2
36.5
°C/W
RθJB
Junction-to-board thermal resistance
49.7
47
44.2
53.6
°C/W
ψJT
Junction-to-top characterization parameter
18.5
18.6
16.8
2.4
°C/W
ψJB
Junction-to-board characterization parameter
49.3
46.5
43.8
52.9
°C/W
(1)
Junction-to-ambient thermal resistance
DB (SSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN74LV374A
–40°C to +85°C
VCC
MIN
VOH
MAX
VCC−0.1
MIN
IOH = −50 µA
2 V to 5.5 V
IOH = −2 mA
2.3 V
2
2
IOH = –8 mA
3V
2.48
2.48
4.5 V
3.8
IOH = −16 mA
VOL
TYP
SN74LV374A
–40°C to +125°C
UNIT
TYP
MAX
VCC−0.1
V
3.8
IOL = 50 µA
2 V to 5.5 V
0.1
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
4.5 V
IOL = 16 mA
0.1
V
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
±1
±1
µA
IOZ
VO = VCC or GND
5.5 V
±5
±5
µA
ICC
VI = VCC or GND , IO = 0
5.5 V
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
µA
Ci
VI = VCC or GND
3.3 V
2.9
2.9
pF
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
SN74LV374A
–40°C to +85°C
TA = 25°C
MAX
MIN
MAX
SN74LV374A
–40°C to +125°C
MIN
TYP
MIN
CL = 15 pF
60(1)
105(1)
50
50
CL = 50 pF
50
85
40
40
MHz
9.7(1)
16.3(1)
1
19
1
20.5
8.9(1)
15.9(1)
1
19
1
20.5
ten
OE
Q
tdis
OE
Q
6.3(1)
12.6(1)
1
15
1
16.5
tpd
CLK
Q
11.8
19.3
1
23
1
24.5
ten
OE
Q
10.9
18.8
1
22
1
23.5
tdis
OE
Q
8.2
17.3
1
19
1
20.5
(1)
CL = 15 pF
CL = 50 pF
2
UNIT
MAX
Q
tsk(o)
6
LOAD
CAPACITANCE
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
LOAD
CAPACITANCE
SN74LV374A
–40°C to +85°C
TA = 25°C
MAX
MIN
SN74LV374A
–40°C to +125°C
MIN
TYP
MAX
MIN
CL = 15 pF
80(1)
150(1)
70
70
CL = 50 pF
55
110
50
50
UNIT
MAX
MHz
Q
6.8(1)
12.7(1)
1
15
1
6.3(1)
11(1)
1
13
1
14
CL = 15 pF
16
ten
OE
Q
tdis
OE
Q
4.7(1)
10.5(1)
1
12.5
1
13.5
tpd
CLK
Q
8.3
16.2
1
18.5
1
19.5
ten
OE
Q
7.7
14.5
1
16.5
1
17.5
tdis
OE
Q
5.9
14
1
16
1
17
CL = 50 pF
tsk(o)
(1)
1.5
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
LOAD
CAPACITANCE
SN74LV374A
–40°C to +85°C
TA = 25°C
MAX
MIN
SN74LV374A
–40°C to +125°C
MIN
TYP
MAX
MIN
CL = 15 pF
130(1)
205(1)
110
110
CL = 50 pF
85
1705
75
75
UNIT
MAX
MHz
Q
4.9(1)
8.1(1)
1
9.5
1
10.5
4.6(1)
7.6(1)
1
9
1
10
ten
OE
Q
CL = 15 pF
tdis
OE
Q
3.4(1)
6.8(1)
1
8
1
9
tpd
CLK
Q
5.9
10.1
1
11.5
1
12.5
ten
OE
Q
5.5
9.6
1
11
1
12
tdis
OE
Q
4
8.8
1
10
1
11
CL = 50 pF
tsk(o)
(1)
1
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.9 Timing Requirements
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 7-1)
TA = 25°C
MIN
SN74LV374A
–40°C to +85°C
MAX
MIN
MAX
SN74LV374A
–40°C to +125°C
MIN
UNIT
MAX
VCC = 2.5 V ± 0.2 V
tw
Pulse duration, CLK high or low
6
7
7
ns
tsu
Setup time, data before CLK↑
5
5.5
6
ns
th
Hold time, data after CLK↑
2.5
2.5
3
ns
VCC = 3.3 V ± 0.3 V
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
5
5.5
5.5
ns
4.5
4.5
5
ns
2
2
2.5
ns
VCC = 5 V ± 0.5 V
tw
Pulse duration, CLK high or low
5
5
5
ns
tsu
Setup time, data before CLK↑
3
3
3.5
ns
th
Hold time, data after CLK↑
2
2
2.5
ns
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6.10 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C (1)
SN74LV374A
PARAMETER
VOL(P)
Quiet output, maximum dynamic VOL
VOL(V)
Quiet output, minimum dynamic VOL
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
MIN
UNIT
TYP
MAX
0.6
0.8
V
−0.5
−0.8
V
2.9
2.9
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.11 Operating Characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF, f = 10 MHz
VCC
TYP
3.3 V
21.1
5V
22.8
UNIT
pF
6.12 Typical Characteristics
Figure 6-1. TPD vs. Temperature at 5 V
8
Figure 6-2. TPD vs. VCC at 25°C
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7 Parameter Measurement Information
7.1
Figure 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV374A devices are octal edge-triggered D-type flip-flops designed for 2 V to 5.5 V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus
drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the
logic levels set up at the data (D) inputs. A buffered output-enable ( OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the
high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied
to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability
of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The output of the device is unknown until the first valid rising clock edge occurs while VCC is within the Section
6.3 range.
8.2 Functional Block Diagram
Figure 8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
Table 8-1 lists the functional modes of the SN74LV374A devices.
Table 8-1. Function Table (Each Flip-Flop)
INPUTS
10
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV374A is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V allowing down translation to the VCC level.
9.2 Typical Application
Figure 9-1 shows how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because
it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
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9.2.2 Detailed Design Procedure
•
•
Recommended Input conditions:
– Rise time and fall time specs see (Δt/ΔV) in Section 6.3.
– Specified High and low levels. See (VIH and VIL) in Section 6.3.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
Recommended output conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above VCC.
9.2.3 Application Curve
Figure 9-2. Switching Characteristics Comparison
12
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9 Power Supply Recommendations
9.1
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section
6.3. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends
a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject
different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass
capacitor should be installed as close as possible to the power terminal for best results.
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10 Layout
10.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that
must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high
or low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense
or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver
has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the
input section of the I.O’s so they also cannot float when disabled.
10.2 Layout Example
Figure 10-1. Layout Example
14
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74LV374A
Click here
Click here
Click here
Click here
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
11.5 Trademarks
All trademarks are the property of their respective owners.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LV374A
15
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV374ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
SN74LV374ADW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
SN74LV374ADWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
SN74LV374ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
SN74LV374ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV374A
Samples
SN74LV374APW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
SN74LV374APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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