SCES226I − APRIL 1999 − REVISED MAY 2005
D Individual Switch Controls
D Extremely Low Input Current
D Ioff Supports Partial-Power-Down Mode
2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
NC
VCC
QK
D 2-V to 5.5-V VCC Operation
D Typical VOLP (Output Ground Bounce)
NC − No internal connection
description/ordering information
ORDERING INFORMATION
PACKAGE†
TA
Tube of 25
SN74LV4040AN
SN74LV4040AN
QFN − RGY
Reel of 1000
SN74LV4040ARGYR
LW040A
Tube of 40
SN74LV4040AD
Reel of 2500
SN74LV4040ADR
SOP − NS
Reel of 2000
SN74LV4040ANSR
74LV4040A
SSOP − DB
Reel of 2000
SN74LV4040ADBR
LW040A
Tube of 90
SN74LV4040APW
Reel of 2000
SN74LV4040APWR
TSSOP − PW
−55°C
125°C
−55
C to 125
C
TOP-SIDE
MARKING
PDIP − N
SOIC − D
−40°C to 85°C
ORDERABLE
PART NUMBER
LV4040A
LW040A
Reel of 250
SN74LV4040APWT
TVSOP − DGV
Reel of 2000
SN74LV4040ADGVR
LW040A
CDIP − J
Tube of 25
SNJ54LV4040AJ
SNJ54LV4040AJ
CFP − W
Tube of 150
SNJ54LV4040AW
SNJ54LV4040AW
LCCC − FK
Tube of 55
SNJ54LV4040AFK
SNJ54LV4040AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$% !%&% '
%()#&% !"))$% & ( *"+,!&% &$- ')"! !%()#
*$!(!&% *$) $ $)# ( $.& %)"#$% &%&) /&))&%0')"!% *)!$%1 $ % %$!$&),0 %!,"$ $%1 ( &,,
*&)$$)POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES226I − APRIL 1999 − REVISED MAY 2005
description/ordering information (continued)
The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
logic diagram (positive logic)
CLR
11
R
CLK
10
R
T
R
R
T
T
4
QF
QG
T
T
T
7
6
5
3
QB
QC
QD
QE
R
R
T
13
QH
R
T
12
POST OFFICE BOX 655303
R
T
14
QI
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
2
R
QA
T
2
R
9
R
T
R
• DALLAS, TEXAS 75265
QJ
T
15
QK
1
QL
SCES226I − APRIL 1999 − REVISED MAY 2005
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance or
power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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3
SCES226I − APRIL 1999 − REVISED MAY 2005
recommended operating conditions (see Note 5)
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MAX
MIN
MAX
2
5.5
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
0
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC × 0.3
5.5
0
VCC
−50
V
VCC × 0.3
5.5
V
VCC
−50
µA
0
V
−2
−6
−6
−12
−12
50
50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
2
2
6
6
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
12
12
200
200
100
100
20
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Input transition rise or fall rate
0.5
VCC × 0.3
VCC × 0.3
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
V
V
0.5
VCC × 0.3
VCC × 0.3
0
UNIT
1.5
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
∆t/∆v
MIN
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
IOL
SN74LV4040A
1.5
Output voltage
IOH
SN54LV4040A
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV4040A
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
MIN
TYP
MIN
IOH = −50 µA
IOH = −2 mA
2 V to 5.5 V
2.3 V
VCC − 0.1
2
VCC − 0.1
2
IOH = −6 mA
IOH = −12 mA
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
IOL = 6 mA
IOL = 12 mA
3V
0.44
0.44
4.5 V
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
IO = 0
UNIT
V
IOL = 50 µA
IOL = 2 mA
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
0
5
5
µA
3.3 V
1.9
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$1% *&$ ( $2$,*#$%- &)&!$)! && &% $)
*$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1
!&%1$ ) !%%"$ $$ *)"! /" %!$-
4
SN74LV4040A
MAX
POST OFFICE BOX 655303
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1.9
pF
SCES226I − APRIL 1999 − REVISED MAY 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
CLK high or low
tw
Pulse duration
tsu
Setup time
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
7
7
7
CLR high
6.5
6.5
6.5
CLR inactive before CLK↓
6.5
6.5
6.5
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
CLK high or low
5
5
5
CLR high
5
5
5
CLR inactive before CLK↓
5
5
5
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
FROM
(INPUT)
TO
(OUTPUT)
fmax
MIN
MAX
SN74LV4040A
MIN
CLK high or low
5
5
5
CLR high
5
5
5
CLR inactive before CLK↓
5
5
5
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
SN54LV4040A
TA = 25°C
TYP
MAX
free-air
SN54LV4040A
ns
range,
SN74LV4040A
MIN
CL = 15 pF
50*
115*
40*
40
CL = 50 pF
40
95
35
35
MAX
UNIT
ns
temperature
LOAD
CAPACITANCE
MIN
MAX
MIN
MAX
UNIT
MHz
tPLH
tPHL
8.7*
19.4*
1*
23*
1
23
CLK
QA
CL = 15 pF
8.7*
19.4*
1*
23*
1
23
tPHL
CLR
Any Q
CL = 15 pF
9.3*
19.9*
1*
24*
1
24
tPLH
tPHL
10.5
24.1
1
28
1
28
CLK
QA
CL = 50 pF
10.5
24.1
1
28
1
28
tPHL
CLR
Any Q
CL = 50 pF
11.7
24.5
1
28
1
28
ns
∆tpd
Qn
Qn+1
CL = 50 pF
1.7
5.9
7
ns
7
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
' ' %()#&% !%!$)% *)"! % $ ()#&2$ )
$1% *&$ ( $2$,*#$%- &)&!$)! && &% $)
*$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1
!&%1$ ) !%%"$ $$ *)"! /" %!$-
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5
SCES226I − APRIL 1999 − REVISED MAY 2005
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
TA = 25°C
TYP
MAX
free-air
temperature
SN54LV4040A
SN74LV4040A
LOAD
CAPACITANCE
MIN
CL = 15 pF
75*
160*
75*
75
CL = 50 pF
55
130
50
50
MIN
MAX
range,
MIN
MAX
UNIT
MHz
tPLH
tPHL
6.1*
11.9*
1*
14*
1
14
CLK
QA
CL = 15 pF
6.1*
11.9*
1*
14*
1
14
tPHL
CLR
Any Q
CL = 15 pF
7.1*
12.8*
1*
15*
1
15
tPLH
tPHL
7.5
15.4
1
17.5
1
17.5
CLK
QA
CL = 50 pF
7.5
15.4
1
17.5
1
17.5
tPHL
CLR
Any Q
CL = 50 pF
9
16.3
1
18.5
1
18.5
ns
∆tpd
Qn
Qn+1
CL = 50 pF
1.2
4.4
5
ns
5
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
free-air
temperature
SN54LV4040A
MIN
MAX
range,
SN74LV4040A
MIN
CL = 15 pF
150*
235*
125*
125
CL = 50 pF
95
185
80
80
MAX
UNIT
MHz
tPLH
tPHL
4.2*
7.3*
1*
8.5*
1
8.5
CLK
QA
CL = 15 pF
4.2*
7.3*
1*
8.5*
1
8.5
tPHL
CLR
Any Q
CL = 15 pF
5.3*
8.6*
1*
10*
1
10
5.3
9.3
1
10.5
1
10.5
ns
ns
tPLH
tPHL
CLK
QA
CL = 50 pF
5.3
9.3
1
10.5
1
10.5
tPHL
CLR
Any Q
CL = 50 pF
6.8
10.6
1
12
1
12
ns
∆tpd
Qn
Qn+1
CL = 50 pF
0.8
3.1
3.5
ns
3.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV4040A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.5
0.8
V
Quiet output, minimum dynamic VOL
−0.5
−0.8
V
VIH(D)
VIL(D)
High-level dynamic input voltage
2.31
V
Low-level dynamic input voltage
0.99
V
VCC
3.3 V
TYP
UNIT
5V
13.1
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
' ' %()#&% !%!$)% *)"! % $ ()#&2$ )
$1% *&$ ( $2$,*#$%- &)&!$)! && &% $)
*$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1
!&%1$ ) !%%"$ $$ *)"! /" %!$-
6
POST OFFICE BOX 655303
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f = 10 MHz
11.9
pF
SCES226I − APRIL 1999 − REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
Input
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV4040AD
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4040A
Samples
SN74LV4040ADBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040ADGVR
ACTIVE
TVSOP
DGV
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040ADR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV4040A
Samples
SN74LV4040AN
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74LV4040AN
Samples
SN74LV4040ANSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV4040A
Samples
SN74LV4040APW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040APWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040APWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040APWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
LW040A
Samples
SN74LV4040ARGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LW040A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of