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SN74LV4051A-Q1
SCLS520E – AUGUST 2003 – REVISED JANUARY 2015
SN74LV4051A-Q1 8-Channel Analog Multiplexer/Demultiplexer
1 Features
3 Description
•
•
This 8-channel CMOS analog multiplexer and
demultiplexer is designed for 2-V to 5.5-V VCC
operation.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
2-V to 5.5-V VCC Operation
Supports Mixed-Mode Voltage Operation on All
Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
The SN74LV4051A handles analog and digital
signals. Each channel permits signals with amplitudes
up to 5.5 V (peak) to be transmitted in either
direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
Device Information(1)
PART NUMBER
PACKAGE
TSSOP (16)
SN74LV4051A-Q1
SOIC (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
10.30 mm × 7.50 mm
9.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
Automotive Infotainment and Cluster
Telematics, eCall
Logic Diagram (Positive Logic)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV4051A-Q1
SCLS520E – AUGUST 2003 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
7
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics VCC = 3.3 V ± 0.3 V .........
Switching Characteristics VCC = 5 V ± 0.5 V ............
Analog Switch Characteristics ..................................
Operating Characteristics..........................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1 Trademarks ........................................................... 14
12.2 Electrostatic Discharge Caution ............................ 14
12.3 Glossary ................................................................ 14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
Changes from Revision D (June 2011) to Revision E
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 5
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5 Pin Configuration and Functions
D, DW, or PW Package
16 Pins
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Y4
1
I (1)
Input to mux
Y6
2
I (1)
Input to mux
(1)
COM
3
O
Y7
4
I (1)
Input to mux
Y5
5
I (1)
Input to mux
INH
6
I (1)
Enables the outputs of the device. Logic low level with turn the outputs on, high level will turn
them off.
GND
7
—
Ground
GND
8
—
Ground
C
9
I
Selector line for outputs (see Device Functional Modes for specific information)
B
10
I
Selector line for outputs (see Device Functional Modes for specific information)
A
11
I
Selector line for outputs (see Device Functional Modes for specific information)
Y3
12
I (1)
Input to mux
Y0
13
I
(1)
Input to mux
Y1
14
I (1)
Input to mux
Y2
15
I (1)
Input to mux
Vcc
16
I
(1)
Output of mux
Device power input
These I/O descriptions represent the device when used as a multiplexer, when this device is operated as a demultiplexer pins Y0-Y7
may be considered outputs (O) and the COM pin may be considered inputs (I).
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Figure 1. Logic Diagram (Positive Logic)
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
–0.5
7V
VCC
Supply voltage
VI
Input voltage (2)
VIO
Switch I/O voltage (2)
IIK
Input clamp current
VI < 0
–20
IIOK
I/O diode current
VIO < 0
–50
IT
Switch through current
VIO = 0 to VCC
–25
Tstg
(1)
(2)
(3)
(3)
UNIT
–0.5
7V
–0.5
VCC +
0.5
V
mA
25
Continuous current through VCC or GND
–50
50
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, and
16)
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
See (1)
MIN
VCC
2 (2)
Supply voltage
VCC = 2 V
VIH
High-level input voltage
NOM
MAX
5.5
UNIT
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
VCC = 2 V
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VIL
Low-level input voltage
VI
Control input voltage
0
5.5
V
VIO
Input/output voltage
0
VCC
V
Δt/Δv
Input transition rise or fall
rate
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
Operating free-air
temperature
TA
Operating free-air
temperature
(1)
(2)
SN74LV4051ATDRQ1,SN74LV4051ATDWRQ1
SN74LV4051ATPWRQ1
SN74LV4051AQPWRQ1
V
ns/V
20
–40
105
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital
signals be transmitted at these low supply voltages.
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6.4 Thermal Information
SN74LV4051A-Q1
THERMAL METRIC (1)
DW
PW
D
16 PINS
16 PINS
16 PINS
RθJB
Junction-to-board thermal resistance
85.1
92.4
113.3
RθJC(top)
Junction-to-case (top) thermal resistance
47.2
52.9
48.1
RθJB
Junction-to-board thermal resistance
49.8
49.5
58.4
ψJT
Junction-to-top characterization parameter
17.8
15.5
6.2
ψJB
Junction-to-board characterization parameter
49.3
49.2
57.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ron
ron(p)
On-state switch
resistance
Peak on-state
resistance
TEST
CONDITIONS
IT = 2 mA,
VI = VCC or GND,
VINH = VIL
(see Figure 2)
IT = 2 mA,
VI = VCC or GND,
VINH = VIL
VCC
TA = 25°C
MIN
TA = -40 to 105°C
MIN
TYP
TA = -40 to 125°C
TYP
MAX
MAX
MIN
TYP
MAX
2.3 V
38
180
225
225
3V
30
150
190
190
4.5 V
22
75
100
100
2.3 V
113
500
600
600
3V
54
180
225
225
4.5 V
31
100
125
125
2.3 V
2.1
30
40
40
3V
1.4
20
30
30
4.5 V
1.3
15
20
20
UNIT
Ω
Ω
Difference in on-state
resistance between
switch
IT = 2 mA,
VI = VCC or GND,
VINH = VIL
Control input current
VI = 5.5 V or GND
0 V to 5.5 V
±0.1
±1
±2
μA
IS(off)
Off-state switch
leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 3)
5.5 V
±0.1
±1
±2
μA
IS(on)
On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 4)
5.5 V
±0.1
±1
±2
μA
ICC
Supply current
VI = VCC or GND
5.5 V
20
40
μA
CIC
Control input
capacitance
f = 10 MHz
3.3 V
2
pF
CIS
Common terminal
capacitance
3.3 V
23.4
pF
COS
Switch terminal
capacitance
3.3 V
5.7
pF
CF
Feedthrough
capacitance
0.5
pF
Δron
II
6
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6.6 Switching Characteristics VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
TA = -40 to
105°C
TA = 25°C
TA = -40 to
125°C
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
Propagation
delay time
COM or Yn
Yn or COM
CL = 50 pF
(see Figure 5)
2.5
9
12
14
ns
Enable delay
time
INH
COM or Yn
CL = 50 pF
(see Figure 6)
5.5
20
25
25
ns
Disable delay
time
INH
COM or Yn
CL = 50 pF
(see Figure 6)
8.8
20
25
25
ns
PARAMETER
MIN
TYP MAX
MIN MAX
MIN
UNIT
MAX
6.7 Switching Characteristics VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted)
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
TA = 25°C
TA = -40 to 105°C
TA = -40 to 125°C
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
COM or
Yn
Yn or
COM
CL = 50 pF
(see Figure 5)
1.5
6
8
10
ns
Enable
delay time
INH
COM or
Yn
CL = 50 pF
(see Figure 6)
4
14
18
18
ns
Disable
delay time
INH
COM or
Yn
CL = 50 pF
(see Figure 6)
6.2
14
18
18
ns
PARAMETER
Propagation
delay time
MIN
TYP MAX
MIN
TYP
MAX
MIN
TYP MAX
UNIT
6.8 Analog Switch Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Frequency response
(switch on)
Crosstalk
(control input to signal
output)
Feedthrough
attenuation
(switch off)
Sine-wave distortion
(1)
(2)
FROM
(INPUT)
COM or Yn
INH
COM or Yn
COM or Yn
TO
(OUTPUT)
Yn or COM
COM or Yn
Yn or COM
Yn or COM
TEST CONDITIONS
VCC
TA = 25°C
MIN
TYP
CL = 50 pF,
RL = 600 Ω,
fin = 1 MHz (sine wave) (1)
(see Figure 7)
2.3 V
20
3V
25
4.5 V
35
CL = 50 pF,
RL = 600 Ω,
fin = 1 MHz (square wave)
(seeFigure 8 )
2.3 V
20
3V
35
4.5 V
60
CL = 50 pF,
RL = 600 Ω,
fin = 1 MHz (2)
(see Figure 9)
2.3 V
–45
CL = 50 pF,
RL = 10 kΩ,
fin = 1 kkHz (sine
wave)
(see Figure 10)
VI = 2 Vp-p
VI = 2.5 Vp-p
VI = 4 Vp-p
3V
–45
4.5 V
–45
2.3 V
0.1%
3V
0.1%
4.5 V
0.1%
MAX
UNIT
MHz
mV
dB
Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
Adjust fin voltage to obtain 0-dBm input.
6.9 Operating Characteristics
VCC = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
TYP
UNIT
5.9
pF
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7 Parameter Measurement Information
=
x
W
–
Figure 2. On-State Resistance Test Circuit
Figure 3. Off-State Switch Leakage-Current Test Circuit
Figure 4. On-State Switch Leakage-Current Test Circuit
8
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Parameter Measurement Information (continued)
W
Figure 5. Propagation Delay Time, Signal Input to Signal Output
W
W
≈
≈
≈
–
≈
Figure 6. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
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Parameter Measurement Information (continued)
m
W
Figure 7. Frequency Response (Switch On)
W
W
Figure 8. Crosstalk (Control Input, Switch Output)
m
W
W
Figure 9. Feedthrough Attenuation (Switch Off)
m
m
W
Figure 10. Sine-Wave Distortion
10
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8 Detailed Description
8.1 Overview
This device is an 8-channel analog multiplexer. A multiplexer is used when several signals must share the same
device or resource. This device allows the selection of one of these signals at a time, for analysis or propagation.
8.2 Functional Block Diagram
8.3 Feature Description
This device contains one 8-channel multiplexer for use in a variety of applications, and can also be configured as
demultiplexer by using the COM pin as an input and the Yx pins as outputs. This device is qualified for
automotive applications and has an extended temperature range of –40°C to 125°C (maximum depends on
package type).
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
INH
C
B
A
ON
CHANNEL
L
L
L
L
Y0
L
L
L
H
Y1
L
L
H
L
Y2
L
L
H
H
Y3
L
H
L
L
Y4
L
H
L
H
Y5
L
H
H
L
Y6
L
H
H
H
Y7
H
X
X
X
None
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A multiplexer is used in applications where multiple signals share a resource. In the example below, several
different sensors are connected to the analog-to-digital converter (ADC) of a microcontroller unit (MCU).
9.2 Typical Application
Figure 11. Example of Multiplexer Use With Analog Sensors and the ADC of an MCU
9.2.1 Design Requirements
Designing with the SN74LV4051A-Q1 device requires a stable input voltage between 2 V (see Recommended
Operating Conditions for details) and 5.5 V. Another important design consideration is the characteristics of the
signal being multiplexed, to ensure no important information is lost due to timing or incompatibility with this
device.
9.2.2 Detailed Design Procedure
Normally, processing eight different analog signals would require eight separate ADCs, but Figure 11 shows how
to achieve this using only one ADC and four GPIOs (general-purpose input/outputs).
12
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10 Power Supply Recommendations
Most systems have a common 3.3-V or 5-V rail that can supply the Vcc pin of this device. If this is not available,
a switched-mode power supply (SMPS) or a low dropout regulator (LDO) can supply this device from a higher
voltage rail.
11 Layout
11.1 Layout Guidelines
TI recommends keeping the signal lines as short and as straight as possible. Incorporation of microstrip or
stripline techniques is also recommended when signal lines are more than 1 inch long. These traces must be
designed with a characteristic impedance of either 50 Ω or 75 Ω,as required by the application. Do not place this
device too close to high-voltage switching components, as they may cause interference.
11.2 Layout Example
Figure 12. Layout Schematic
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CLV4051ATDWRG4Q1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
L4051AQ
CLV4051ATPWRG4Q1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
L4051AQ
SN74LV4051AQPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
4051AQ1
SN74LV4051ATDRQ1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
L4051AQ
SN74LV4051ATDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
L4051AQ
SN74LV4051ATPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
L4051AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4051A-Q1 :
• Catalog: SN74LV4051A
• Enhanced Product: SN74LV4051A-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CLV4051ATDWRG4Q1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
CLV4051ATPWRG4Q1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV4051AQPWRQ1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV4051ATDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
SN74LV4051ATPWRQ1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLV4051ATDWRG4Q1
SOIC
DW
16
2000
350.0
350.0
43.0
CLV4051ATPWRG4Q1
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV4051AQPWRQ1
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV4051ATDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
SN74LV4051ATPWRQ1
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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